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公开(公告)号：US10348480B2
公开(公告)日：2019-07-09
申请号：US15799016
申请日：2017-10-31
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Yikui Jen Dong , Arash Zargaran-Yazd
Abstract: A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams.
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公开(公告)号：US20170331648A1
公开(公告)日：2017-11-16
申请号：US15582182
申请日：2017-04-28
Applicant: Rambus Inc.
Inventor： Yikui Jen Dong
CPC classification number: H04L25/03057 , H04B1/16 , H04B10/69 , H04B10/695 , H04L25/0272 , H04L25/0292
Abstract: An on-chip AC coupled receiver with offset calibration. The receiver includes AC coupling circuitry to couple a differential input signal into a coupled differential signal having a first signal and a second signal. The receiver includes a first comparator to generate a first error signal indicative of whether a first reference signal is greater or smaller than a signal derived from the coupled differential signal. The receiver includes a second comparator to generate a second error signal indicative of whether a second reference signal is greater or smaller than the signal derived from the coupled differential signal. The receiver further includes feedback circuitry to adjust a voltage offset between the first signal and the second signal of the coupled differential signal based on the first error signal and the second error signal.
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13.发明授权On-chip AC coupled receiver with real-time linear baseline-wander compensation 有权具有实时线性基线漂移补偿的片上AC耦合接收器公开(公告)号：US09491008B2
公开(公告)日：2016-11-08
申请号：US14789794
申请日：2015-07-01
Applicant: Rambus Inc.
Inventor： Yikui Jen Dong
CPC classification number: H04L25/03019 , H03K5/007 , H04L25/0292 , H04L25/0296 , H04L25/06 , H04L47/50
Abstract: An on-chip AC coupled receiver with baseline wander compensation. The receiver may be used for either single ended or differential signals. The receiver includes an input terminal to receive an input signal. AC coupling circuitry is between the input terminal and a node and couples the input signal into a coupled signal at the node. A control loop senses low frequency signal content at the node and uses a linear buffer in adjusting the coupled signal at the node based on the low frequency signal content. The operation of the control loop compensates for potential baseline wander in the coupled signal. An input stage to recovers data from the coupled signal at the node.
Abstract translation: 具有基线漂移补偿的片上AC耦合接收器。 接收机可以用于单端或差分信号。 接收机包括用于接收输入信号的输入端。 AC耦合电路位于输入端和节点之间，并将输入信号耦合到节点处的耦合信号。 控制回路感测节点处的低频信号内容，并且基于低频信号内容使用线性缓冲器来调整节点处的耦合信号。 控制环路的操作补偿了耦合信号中潜在的基线漂移。 用于从节点处的耦合信号恢复数据的输入级。
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公开(公告)号：US11211960B2
公开(公告)日：2021-12-28
申请号：US17114782
申请日：2020-12-08
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Yikui Jen Dong , Arash Zargaran-Yazd , Wendemagegnehu Beyene
Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.
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公开(公告)号：US10892791B2
公开(公告)日：2021-01-12
申请号：US16680859
申请日：2019-11-12
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Yikui Jen Dong , Arash Zargaran-Yazd , Wendemagegnehu Beyene
Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.
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Patent Agency Ranking
公开(公告)号：US10530616B2
公开(公告)日：2020-01-07
申请号：US15761938
申请日：2016-08-03
Applicant: RAMBUS INC.
Inventor： Yikui Jen Dong
IPC: H04L25/03
Abstract: A transmitting device includes an output node, at least one driver circuit and transition equalization circuitry. The driver circuit drives an output data signal including a data transition onto the output node. The output of the transition equalization circuitry is coupled to the output node. The transition equalization circuitry begins to drive the output node at the data transition and ends driving of the output node a pre-determined delay after beginning to drive the output node. The transition equalization circuitry drives the output node by injecting current onto the output node if the data transition is a positive transition, and sinking current from the output node if the data transition is a negative transition.
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公开(公告)号：US10516427B2
公开(公告)日：2019-12-24
申请号：US15755255
申请日：2016-10-12
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Yikui Jen Dong , Arash Zargaran-Yazd , Wendemagegnehu Beyene
Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.
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公开(公告)号：US10027516B2
公开(公告)日：2018-07-17
申请号：US15582182
申请日：2017-04-28
Applicant: Rambus Inc.
Inventor： Yikui Jen Dong
Abstract: An on-chip AC coupled receiver with offset calibration. The receiver includes AC coupling circuitry to couple a differential input signal into a coupled differential signal having a first signal and a second signal. The receiver includes a first comparator to generate a first error signal indicative of whether a first reference signal is greater or smaller than a signal derived from the coupled differential signal. The receiver includes a second comparator to generate a second error signal indicative of whether a second reference signal is greater or smaller than the signal derived from the coupled differential signal. The receiver further includes feedback circuitry to adjust a voltage offset between the first signal and the second signal of the coupled differential signal based on the first error signal and the second error signal.
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公开(公告)号：US09832009B2
公开(公告)日：2017-11-28
申请号：US15212514
申请日：2016-07-18
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Yikui Jen Dong , Arash Zargaran-Yazd
CPC classification number: H04L7/0087 , H03K7/02 , H03L7/00 , H04L7/0025 , H04L7/0337 , H04L25/4917
Abstract: A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams.
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公开(公告)号：US09794088B2
公开(公告)日：2017-10-17
申请号：US15290275
申请日：2016-10-11
Applicant: Rambus Inc.
Inventor： Yikui Jen Dong
IPC: H03K5/007 , H04L25/03 , H04L25/02 , H04L12/863 , H04L25/06
CPC classification number: H04L25/03019 , H03K5/007 , H04L25/0292 , H04L25/0296 , H04L25/06 , H04L47/50
Abstract: An on-chip AC coupled receiver with baseline wander compensation. The receiver may be used for either single ended or differential signals. The receiver includes an input terminal to receive an input signal. AC coupling circuitry is between the input terminal and a node and couples the input signal into a coupled signal at the node. A control loop senses low frequency signal content at the node and uses a linear buffer in adjusting the coupled signal at the node based on the low frequency signal content. The operation of the control loop compensates for potential baseline wander in the coupled signal. An input stage to recovers data from the coupled signal at the node.
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