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    Low power static random access memory
    11.
    发明授权
    Low power static random access memory 有权
    低功率静态随机存取存储器

    公开(公告)号：US08982610B2

    公开(公告)日：2015-03-17

    申请号：US13750943

    申请日：2013-01-25

    Applicant: Raytheon Company

    Inventor： Micky Harris ,  Wasim Khaled

    IPC: G11C11/00 ,  G11C11/419 ,  G11C7/12 ,  G11C11/412 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/412 ,  G11C11/4125 ,  G11C11/418

    Abstract: A bit line driver for a static random access memory (SRAM) cell including: a first voltage supply for supplying a first voltage; a second voltage supply for supplying a second voltage that is less than the first voltage; a write circuit to drive a bit line and an inverse bit line when writing to the SRAM cell; and a pre-charge circuit to pre-charge the bit line and the inverse bit line before reading the content of the SRAM cell. The bit line driver supplies a voltage less than the first voltage by a threshold voltage of one transistor to the bit line or the inverse bit line when the bit line driver drives the bit line or the inverse bit line to a high state.

    Abstract translation: 一种用于静态随机存取存储器（SRAM）单元的位线驱动器，包括：用于提供第一电压的第一电压源; 用于提供小于所述第一电压的第二电压的第二电压源; 写入电路以写入SRAM单元时驱动位线和反向位线; 以及在读取SRAM单元的内容之前对位线和反位线进行预充电的预充电电路。 当位线驱动器将位线或反位线驱动到高电平状态时，位线驱动器将一个晶体管的阈值电压小于第一电压的电压提供给位线或反位线。

    Per-pixel detector bias control
    12.
    发明授权
    Per-pixel detector bias control 有权

    公开(公告)号：US11561132B2

    公开(公告)日：2023-01-24

    申请号：US16892430

    申请日：2020-06-04

    Applicant: RAYTHEON COMPANY

    Inventor： Eric J. Beuville ,  Micky Harris ,  Ryan Boesch ,  Christian M. Boemler

    IPC: G01J1/46 ,  G01J5/34 ,  G01J1/44

    Abstract: A pixel includes a detector that changes its operating characteristics based on incident energy, an integration capacitor arranged to discharge stored charge through the detector based on changes in the operating characteristics, and an floating gate injection device disposed between the photo-diode and the integration capacitor that controls flow of the charge from the integration capacitor to the detector. The floating gate injection device has a gate, a source electrically coupled to the detector at a first node, and a drain electrically coupled to the integration capacitor. The gate has a control voltage (VT) stored therein to set to a per-pixel bias gate voltage to control a detector bias voltage of the detector at the first node.

    STACKED SENSOR WITH INTEGRATED CAPACITORS
    13.
    发明申请
    STACKED SENSOR WITH INTEGRATED CAPACITORS 审中-公开

    公开(公告)号：US20200168651A1

    公开(公告)日：2020-05-28

    申请号：US16201633

    申请日：2018-11-27

    Applicant: RAYTHEON COMPANY

    Inventor： Neil R. Malone ,  Sean P. Kilcoyne ,  Micky Harris

    IPC: H01L27/146

    Abstract: A three-dimensional (3D) stack is provided and includes a capacitor layer and an integrated circuit (IC) layer. The capacitor layer includes capacitors and capacitor layer connectors respectively communicative with corresponding capacitors. The IC layer is stacked vertically with the capacitor layer and is hybridized to a detector. The IC layer includes IC layer connectors respectively communicative with corresponding capacitor layer connectors.

    PER-PIXEL DETECTOR BIAS CONTROL
    14.
    发明申请
    PER-PIXEL DETECTOR BIAS CONTROL 审中-公开

    公开(公告)号：US20200066781A1

    公开(公告)日：2020-02-27

    申请号：US16549069

    申请日：2019-08-23

    Applicant: RAYTHEON COMPANY

    Inventor： Eric J. Beuville ,  Micky Harris ,  Ryan Boesch ,  Christian M. Boemler

    IPC: H01L27/146 ,  H01L27/148 ,  H04N5/359

    Abstract: A pixel includes a photo-diode, an integration capacitor arranged to receive a photo current from the photo-diode and to store charge developed from the photo current; and an injection transistor disposed between the photo-diode and the integration capacitor that controls flow of the photo current from the photo-diode to the integration capacitor, the injection transistor having a gate, a source electrically coupled to the photo-diode at a first node, and a drain electrically coupled to the integration capacitor. The injection transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) FET having its gate set to a SONOS gate voltage to control a detector bias voltage of the photo-diode at the first node.

    Per-pixel detector bias control
    17.
    发明授权
    Per-pixel detector bias control 有权

    公开(公告)号：US11626445B2

    公开(公告)日：2023-04-11

    申请号：US16549069

    申请日：2019-08-23

    Applicant: RAYTHEON COMPANY

    Inventor： Eric J. Beuville ,  Micky Harris ,  Ryan Boesch ,  Christian M. Boemler

    IPC: H01L27/146 ,  H04N5/359 ,  H01L27/148

    Abstract: A pixel includes a photo-diode, an integration capacitor arranged to receive a photo current from the photo-diode and to store charge developed from the photo current; and an injection transistor disposed between the photo-diode and the integration capacitor that controls flow of the photo current from the photo-diode to the integration capacitor, the injection transistor having a gate, a source electrically coupled to the photo-diode at a first node, and a drain electrically coupled to the integration capacitor. The injection transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) FET having its gate set to a SONOS gate voltage to control a detector bias voltage of the photo-diode at the first node.

    DIGITAL PIXEL HAVING HIGH SENSITIVITY AND DYNAMIC RANGE
    18.
    发明申请
    DIGITAL PIXEL HAVING HIGH SENSITIVITY AND DYNAMIC RANGE 有权

    公开(公告)号：US20210377470A1

    公开(公告)日：2021-12-02

    申请号：US16890483

    申请日：2020-06-02

    Applicant: Raytheon Company

    Inventor： Neil R. Malone ,  Micky Harris ,  Adam M. Kennedy ,  George Paloczi ,  John L. Vampola ,  Christian M. Boemler

    IPC: H04N5/355 ,  H04N5/378 ,  H04N5/3745

    Abstract: A digital pixel includes a capacitive transimpedence amplifier (CTIA) coupled to a photodiode that receives an electrical charge and output an integration voltage. An integration capacitor coupled to the CTIA accumulates the integration voltage over an integration period. A comparator compares the accumulated integration voltage with a threshold voltage and generates a control signal at a first level each time the accumulated integration voltage is greater than the threshold voltage. A charge subtraction circuit receives the control signal at the first level and discharges the accumulated integration voltage each time the control signal at the first level is received from the comparator. An analog or digital counter receives the control signal at the first level and adjusts a counter value each time the control signal is received from the comparator. An output interface communicates the counter value to an image processing circuit at an end of the integration period.

    DIGITAL IN-PIXEL READ-OUT INTEGRATED CIRCUIT INCLUDING RESIDUE-TO-COUNTER CALIBRATION
    19.
    发明申请
    DIGITAL IN-PIXEL READ-OUT INTEGRATED CIRCUIT INCLUDING RESIDUE-TO-COUNTER CALIBRATION 审中-公开

    公开(公告)号：US20200382733A1

    公开(公告)日：2020-12-03

    申请号：US16427968

    申请日：2019-05-31

    Applicant: RAYTHEON COMPANY

    Inventor： Michael J. Batinica ,  Elina R. Glaretas ,  Micky Harris

    IPC: H04N5/378 ,  H04N5/353

    Abstract: A digital pixel circuit includes a unit cell configured to accumulate an electrical charge during a frame. The electrical charge is proportional to a light intensity of a light signal that is detected at a location in a field of view of the unit cell. An image processing unit is in signal communication with the unit cell. The image processing unit is configured to determine a total charge based on a plurality of accumulated charges over a plurality of sequential frames, and to determine an indication of the light intensity of light at the location based on the total charge. The unit cell is configured to operate in a first mode to accumulate the electrical charges over the plurality of sequential frames, and a second mode to perform a calibration operation that calibrates the unit cell based on the electrical charge accumulated during a single frame among the plurality of frames.

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