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    DETECTOR ARRAYS WITH ELECTRONICALLY ADJUSTABLE DETECTOR POSITIONS
    1.
    发明申请
    DETECTOR ARRAYS WITH ELECTRONICALLY ADJUSTABLE DETECTOR POSITIONS 审中-公开
    检测器阵列与电子可调谐探测器位置

    公开(公告)号：US20160331265A1

    公开(公告)日：2016-11-17

    申请号：US14711042

    申请日：2015-05-13

    申请人： Raytheon Company

    发明人： Matthew D. Chambers ,  John L. Vampola ,  Micky Harris

    IPC分类号： A61B5/05

    CPC分类号： A61B5/05 ,  A61B5/7203 ,  A61B2562/046 ,  A61B2576/00 ,  H01L27/14856 ,  H04N5/347 ,  H04N5/37206 ,  H04N5/3743

    摘要： A system including a detector array configured to receive electromagnetic (EM) radiation from a target object, the detector array having one or more detectors is disclosed. The system also includes a readout integrated circuit and one or more processors. The readout integrated circuit has a circuit comprising a number of detector boundary selection components, each one of the number of detector boundary selection components configured to select or adjust a detector boundary from least one of a sub-column boundary or an adjustable boundary.

    摘要翻译： 一种包括被配置为从目标物体接收电磁（EM）辐射的检测器阵列的系统，所述检测器阵列具有一个或多个检测器。 该系统还包括读出集成电路和一个或多个处理器。 读出集成电路具有包括多个检测器边界选择部件的电路，每个检测器边界选择部件中的每一个被配置为从子列边界或可调边界中的至少一个选择或调整检测器边界。

    MOSAIC FOCAL PLANE ARRAY
    2.
    发明申请
    MOSAIC FOCAL PLANE ARRAY 有权

    公开(公告)号：US20220310690A1

    公开(公告)日：2022-09-29

    申请号：US17212085

    申请日：2021-03-25

    申请人： Raytheon Company

    发明人： David J. Gulbransen ,  Sean P. Kilcoyne ,  Eric Miller ,  Matthew D. Chambers ,  Eric J. Beuville ,  Andrew E. Gin ,  Adam M. Kennedy

    IPC分类号： H01L27/146 ,  H01L21/66 ,  H01L23/00

    摘要： A focal plane array includes a mosaic integrated circuit device having a plurality of discrete integrated circuit tiles mounted on a motherboard. The focal plane array includes an optically continuous detector array electrically connected to the mosaic integrated circuit device with an interposer disposed therebetween. The interposer is configured to adjust a pitch of the continuous detector array to match a pitch of each of the plurality of discrete integrated circuit tiles so that the optical gaps between each of the plurality of integrated circuit tiles on the motherboard are minimized and the detector array is optically continuous, having high yield over the large format focal plane array.