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公开(公告)号：US06226217B1
公开(公告)日：2001-05-01
申请号：US09507207
申请日：2000-02-18
IPC分类号： G11C800
CPC分类号： G11C11/412
摘要： A system and method are disclosed which provide a register structure enabling a dual-ended write thereto with a minimum amount of high-level metal tracks and components, thereby minimizing the amount of surface area required for such register structure. A data carrier (e.g., a BIT line) is utilized to carry a data value desired to be written from a port to a memory cell of a register structure. Such a data carrier may be implemented as a high-level metal track that spans multiple register structures to enable a port the capability of writing to such multiple register structures. Also, a line for triggering a write operation for a port (e.g., a WORD line) is implemented, and such a triggering line may be implemented as a high-level metal track. A preferred embodiment provides a register structure that includes a dual-ended write mechanism. In a preferred embodiment, a complementary data carrier for a port is generated locally within a register structure. Thus, a preferred embodiment minimizes the number of high-level metal tracks required because a complementary data carrier for each port is not required to be implemented as a high-level metal track. Furthermore, a preferred embodiment generates a complementary data carrier for a port locally within the register structure in a manner that does not require an inverter. More specifically, a preferred embodiment implements a NFET that is arranged in a manner to generate the necessary complementary data carrier (e.g., NBIT line) for performing a dual-ended write.
摘要翻译： 公开了一种系统和方法，其提供了一种寄存器结构，其能够以最小量的高级金属轨道和部件实现双端写入，从而最小化这种寄存器结构所需的表面积的量。 使用数据载体（例如，BIT线）将希望从端口写入的数据值传送到寄存器结构的存储单元。 这样的数据载体可以实现为跨越多个寄存器结构的高级金属轨道，以使端口能够写入这样的多个寄存器结构。 而且，实现用于触发端口（例如，WORD线）的写操作的线，并且这样的触发线可以被实现为高级金属轨道。 优选实施例提供包括双端写机构的寄存器结构。 在优选实施例中，用于端口的互补数据载体在寄存器结构内本地生成。 因此，优选实施例使得需要的高级金属轨道的数量最小化，因为用于每个端口的互补数据载体不需要被实现为高级金属轨道。 此外，优选实施例以不需要逆变器的方式在寄存器结构内本地生成用于端口的互补数据载体。 更具体地，优选实施例实施NFET，其以以生成用于执行双端写入的必要的互补数据载体（例如，NBIT线）的方式被布置。
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公开(公告)号：US06873565B1
公开(公告)日：2005-03-29
申请号：US10684019
申请日：2003-10-10
IPC分类号： G11C11/41 , G11C8/16 , G11C11/412 , G11C7/02 , G11C7/10 , G11C7/24 , G11C11/417
CPC分类号： G11C11/4125 , G11C8/16
摘要： In a preferred embodiment, the invention provides a circuit and method for improving the soft error rate in a dual-port read SRAM cell. A write-only transfer device is connected to a cross-coupled latch, a first wordline, and a first bitline. A first read-only transfer device is connected to a second bitline, a second wordline, and a first pull-down device. A second read-only transfer device is connected to the first bitline, the first wordline, and a second pull-down device. A clear memory transfer device is connected to the cross-coupled latch, a third bitline, and a third pull-down device. This configuration allows a reduction in the size of a dual-port SRAM cell with little or no reduction in the read access time of the cell. The reduction in size also reduces SER by reducing the cross-sectional, p/n junction area exposed to radiation.
摘要翻译： 在优选实施例中，本发明提供了一种用于改善双端口读SRAM单元中的软错误率的电路和方法。 只写传输设备连接到交叉耦合锁存器，第一字线和第一位线。 第一只读传送装置连接到第二位线，第二字线和第一下拉装置。 第二只读传送设备连接到第一位线，第一字线和第二下拉设备。 清晰的存储器传输装置连接到交叉耦合的锁存器，第三位线和第三下拉器件。 这种配置允许减小双端口SRAM单元的尺寸，而小单元的读取访问时间几乎没有或没有减小。 通过减少暴露于辐射的横截面的p / n结面积，尺寸的减小也降低了SER。
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公开(公告)号：US06550034B1
公开(公告)日：2003-04-15
申请号：US09505549
申请日：2000-02-17
IPC分类号： G01R3128
摘要： A system and method are disclosed which provide a built-in self test (BIST) for a content addressable memory (CAM) structure. In a preferred embodiment, an integrated circuit (chip) comprises a CAM structure that is accessible by a processor to satisfy memory access requests and a BIST implemented within such chip, which enables testing the integrity of the CAM structure. Such a preferred embodiment comprises a BIST that enables testing the integrity of the CAM structure that does not require circuitry for reading memory data out of the CAM structure. A preferred embodiment can also be utilized for testing a random access memory structure. In a preferred embodiment, a CAM BIST comprises logic capable of generating test values (e.g., a test pattern), a shift register that temporarily stores the test values generated by the logic, and compare circuitry that determines whether a test value matches an entry within the CAM structure.
摘要翻译： 公开了一种为内容可寻址存储器（CAM）结构提供内置自检（BIST）的系统和方法。 在优选实施例中，集成电路（芯片）包括可由处理器访问以满足存储器访问请求的CAM结构和在该芯片内实现的BIST，其能够测试CAM结构的完整性。 这样的优选实施例包括BIST，其能够测试不需要用于从CAM结构读出存储器数据的电路的CAM结构的完整性。 优选实施例也可用于测试随机存取存储器结构。 在优选实施例中，CAM BIST包括能够生成测试值（例如，测试模式）的逻辑，临时存储由逻辑产生的测试值的移位寄存器，以及确定测试值是否匹配于逻辑内的条目的比较电路 CAM结构。
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公开(公告)号：US06539466B1
公开(公告)日：2003-03-25
申请号：US09510276
申请日：2000-02-21
IPC分类号： G06F1210
CPC分类号： G11C8/18 , G06F12/1027 , G11C15/00 , G11C15/04
摘要： A self-timed translation lookaside buffer (TLB) is disclosed that utilizes a two-level match scheme to trigger the evaluation of whether a match is achieved for a received virtual address within the TLB. The first level is referred to as the local match, and the second level is referred to as the global match. An entry of a TLB comprises groups of bits, with each group coupled to a separate local match line. Each of the local match lines of an entry is coupled to a global match line, which is initially set to a high voltage level and discharges to a low voltage level if any of the local match lines indicate a mismatch for their respective group. Accordingly, when the global match lines are evaluated, if the global match line has a high voltage level it indicates that the associated TLB entry matches the virtual address, otherwise the global match line indicates a mismatch for the entry. Multiple global match lines are evaluated to trigger a memory access for a matching entry. More specifically, in a preferred embodiment, a pair of neighboring global match lines are input to a NAND gate, the output of which triggers the evaluation of whether a match is achieved for either entry.
摘要翻译： 公开了一种自定义翻译后备缓冲器（TLB），其利用两级匹配方案来触发对TLB内接收到的虚拟地址是否实现匹配的评估。 第一级称为本地匹配，第二级称为全局匹配。 TLB的条目包括比特组，每个组耦合到单独的本地匹配线。 条目的每个局部匹配线被耦合到全局匹配线，其被初始设置为高电压电平，并且如果任何局部匹配线指示其相应组的不匹配，则放电到低电压电平。 因此，当评估全局匹配线时，如果全局匹配线具有高电压电平，则指示相关联的TLB条目与虚拟地址匹配，否则全局匹配线指示条目的不匹配。 评估多个全局匹配行以触发匹配条目的内存访问。 更具体地，在优选实施例中，一对相邻的全局匹配线被输入到NAND门，其输出触发评估对于任一条目是否实现匹配。
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公开(公告)号：US06507892B1
公开(公告)日：2003-01-14
申请号：US09510285
申请日：2000-02-21
IPC分类号： G06F1300
CPC分类号： G06F12/0857 , G06F12/0831
摘要： The inventive cache processes multiple access requests simultaneously by using separate queuing structures for data and instructions. The inventive cache uses ordering mechanisms that guarantee program order when there are address conflicts and architectural ordering requirements. The queuing structures are snoopable by other processors of a multiprocessor system. The inventive cache has a tag access bypass around the queuing structures, to allow for speculative checking by other levels of cache and for lower latency if the queues are empty. The inventive cache allows for at least four accesses to be processed simultaneously. The results of the access can be sent to multiple consumers. The multiported nature of the inventive cache allows for a very high bandwidth to be processed through this cache with a low latency.
摘要翻译： 本发明的高速缓存通过使用用于数据和指令的单独的排队结构同时处理多个访问请求。 本发明的高速缓存使用排序机制，当存在地址冲突和架构排序要求时，保证程序顺序。 排队结构可以被多处理器系统的其他处理器窥探。 本发明的高速缓存具有围绕排队结构的标签访问绕过，以允许其他级别的高速缓存的推测性检查以及如果队列为空，则延迟较低。 本发明的缓存允许同时处理至少四个访问。 访问的结果可以发送给多个消费者。 本发明的高速缓存的多端口性质允许通过具有低等待时间的该缓存来处理非常高的带宽。
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公开(公告)号：US06208565B1
公开(公告)日：2001-03-27
申请号：US09507333
申请日：2000-02-18
IPC分类号： G11C700
CPC分类号： G11C8/16
摘要： A system and method are disclosed which provide a pulse write mechanism to enable a port to write to a register structure without requiring a large amount of circuitry. One or more ports may be coupled to a register structure in a manner that enables the ports to write data to the register structure without requiring a large amount of circuitry. The ports may be coupled to the register structure in a manner that enables them the capability of reading data from the register structure without requiring additional circuitry beyond that required for a write operation. A preferred embodiment implements a single-ended write structure, wherein a data carrier (e.g., BIT line) is utilized to carry a data value desired to be written for a port. A preferred embodiment comprises a write pulse mechanism, such as a NFET, capable of setting the memory cell to an initial value before performing a write thereto. Before performing a write operation to a memory cell, the write pulse signal is fired causing the write pulse mechanism to initialize the memory cell to a high voltage value. If the value of the BIT line is the same as the value to which the memory cell was initialized, the memory access mechanism enables the memory cell to remain at such value. However, if the value of the BIT line is different than the initial value of the memory cell, the memory access mechanism transitions the memory cell to the value of the BIT line.
摘要翻译： 公开了一种提供脉冲写入机制以使端口能够写入寄存器结构而不需要大量电路的系统和方法。 一个或多个端口可以以使得端口能够将数据写入寄存器结构而不需要大量电路的方式耦合到寄存器结构。 端口可以以使得它们能够从寄存器结构读取数据的能力而不需要超出写入操作所需的额外电路的方式耦合到寄存器结构。 优选实施例实现单端写入结构，其中使用数据载体（例如，BIT线）来承载期望为端口写入的数据值。 优选实施例包括能够在执行写入之前将存储器单元设置为初始值的写入脉冲机制，例如NFET。 在对存储单元执行写入操作之前，写入脉冲信号被触发，使得写入脉冲机制将存储单元初始化为高电压值。 如果BIT行的值与存储单元初始化的值相同，则存储器访问机制使存储单元保持在这样的值。 但是，如果BIT行的值与存储单元的初始值不同，则存储器访问机制将存储单元转换为BIT行的值。
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