公开(公告)号：US06285579B1

公开(公告)日：2001-09-04

申请号：US09505561

申请日：2000-02-17

申请人： Reid James Riedlinger ,  Donald R. Weiss

发明人： Reid James Riedlinger ,  Donald R. Weiss

IPC分类号： G11C1100

CPC分类号： G11C11/419

摘要： A system and method are provided which enable a data carrier, such as a BIT line, to be held to a desired value while performing a memory access (e.g., a read or write operation) of SRAM in an efficient manner. In a preferred embodiment, cross-coupled PFETs are implemented to hold the BIT line to a desired value during a memory access of SRAM. As a result, a preferred embodiment enables a BIT line to transition from a high voltage value to a low voltage value free from conflict. That is, in a preferred embodiment, a holder PFET is not attempting to hold the BIT line high, while the SRAM or outside source (e.g., a “writing source”) is attempting to drive the BIT line to a low voltage value. Also, in a preferred embodiment, the BIT and NBIT lines (i.e., a complementary data carrier) can be driven to “true” low and “true” high voltage values. Accordingly, in a preferred embodiment, complex circuitry, such as a sense amp, is not required to detect whether a value on the lines is a logic 0 or logic 1. Therefore, a preferred embodiment enables memory access requests (e.g., read and write operations) to be serviced in a more timely manner than is achieved utilizing prior art implementations. Furthermore, a preferred embodiment requires less power consumption than is required for prior art implementations. Moreover, a preferred embodiment utilizes fewer components, and therefore consumes less surface area than in prior art implementations.

摘要翻译： 提供了一种系统和方法，其使数据载体（例如BIT线）能够以有效的方式执行SRAM的存储器访问（例如，读或写操作）而被保持到期望值。 在优选实施例中，实现交叉耦合PFET以在SRAM的存储器访问期间将BIT线保持在期望值。 结果，优选实施例使得BIT线能够从高电压值转变为没有冲突的低电压值。 也就是说，在优选实施例中，保持器PFET没有试图将BIT线保持为高电平，而SRAM或外部源（例如，“写入源”）正试图将BIT线驱动到低电压值。 此外，在优选实施例中，可以将BIT和NBIT线（即，互补数据载体）驱动为“真实”低电平和“真实”高电压值。 因此，在优选实施例中，不需要诸如读出放大器的复杂电路来检测线路上的值是逻辑0还是逻辑1.因此，优选实施例使得存储器访问请求（例如，读取和写入 操作）比使用现有技术实现所实现的更及时地进行服务。 此外，优选实施例比现有技术实现所需的功耗要低。 此外，优选实施例利用较少的部件，因此消耗比现有技术实施方式更少的表面积。

公开(公告)号：US06550034B1

公开(公告)日：2003-04-15

申请号：US09505549

申请日：2000-02-17

申请人： Reid James Riedlinger ,  Donald R. Weiss

发明人： Reid James Riedlinger ,  Donald R. Weiss

IPC分类号： G01R3128

CPC分类号： G11C29/14 ,  G11C15/00

摘要： A system and method are disclosed which provide a built-in self test (BIST) for a content addressable memory (CAM) structure. In a preferred embodiment, an integrated circuit (chip) comprises a CAM structure that is accessible by a processor to satisfy memory access requests and a BIST implemented within such chip, which enables testing the integrity of the CAM structure. Such a preferred embodiment comprises a BIST that enables testing the integrity of the CAM structure that does not require circuitry for reading memory data out of the CAM structure. A preferred embodiment can also be utilized for testing a random access memory structure. In a preferred embodiment, a CAM BIST comprises logic capable of generating test values (e.g., a test pattern), a shift register that temporarily stores the test values generated by the logic, and compare circuitry that determines whether a test value matches an entry within the CAM structure.

摘要翻译： 公开了一种为内容可寻址存储器（CAM）结构提供内置自检（BIST）的系统和方法。 在优选实施例中，集成电路（芯片）包括可由处理器访问以满足存储器访问请求的CAM结构和在该芯片内实现的BIST，其能够测试CAM结构的完整性。 这样的优选实施例包括BIST，其能够测试不需要用于从CAM结构读出存储器数据的电路的CAM结构的完整性。 优选实施例也可用于测试随机存取存储器结构。 在优选实施例中，CAM BIST包括能够生成测试值（例如，测试模式）的逻辑，临时存储由逻辑产生的测试值的移位寄存器，以及确定测试值是否匹配于逻辑内的条目的比较电路 CAM结构。

公开(公告)号：US20080144367A1

公开(公告)日：2008-06-19

申请号：US11639865

申请日：2006-12-15

申请人： Michael A. Dreesen ,  John J. Wuu ,  Donald R. Weiss

发明人： Michael A. Dreesen ,  John J. Wuu ,  Donald R. Weiss

IPC分类号： G11C11/4091 ,  G11C7/06

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C11/404 ,  G11C11/4091 ,  G11C2207/063 ,  G11C2211/4016

摘要： A memory device includes a memory array and a sense amplifier. The memory array includes a floating body cell configured to store a bit value. The sense amplifier includes a bit output configured to provide an output voltage representative of the bit value and a reference source configured to provide a reference voltage. The sense amplifier further includes a current mirror configured to provide a current to the first floating body cell based on the reference voltage, and a differential amplifier circuit configured to determine the output voltage based on the reference voltage and a voltage across the floating body cell resulting from application of the current to the floating body cell.

摘要翻译： 存储器件包括存储器阵列和读出放大器。 存储器阵列包括被配置为存储位值的浮体单元。 感测放大器包括被配置为提供表示比特值的输出电压的位输出和被配置为提供参考电压的参考源。 感测放大器还包括电流镜，其被配置为基于参考电压向第一浮动体单元提供电流;以及差分放大器电路，其被配置为基于参考电压和浮体电池两端的电压来确定输出电压 从电流应用到浮体细胞。

公开(公告)号：US5787041A

公开(公告)日：1998-07-28

申请号：US724204

申请日：1996-10-01

申请人： J. Michael Hill ,  Donald R. Weiss

发明人： J. Michael Hill ,  Donald R. Weiss

IPC分类号： G11C7/00 ,  G11C7/10

CPC分类号： G11C7/00 ,  G11C7/1042

摘要： An improved random access memory (RAM) system enhances the speed and reduces power dissipation and logic complexity associated with a RAM. The RAM system includes first and second pluralities of RAM cell columns. Each of the columns includes (1) at least one RAM cell, each RAM cell configured to read and write a respective logic state and (2) bit and nbit connections (differential and complimentary) connected to each of the RAM cells. A first multiplexer is designed to multiplex the bit and nbit connections of the first plurality of RAM cell columns. A second multiplexer is configured to multiplex the bit and nbit connections of the second plurality of columns. Decode logic controls the first and second multiplexers, and the decode logic accesses a particular column and cell in one of the first and second pluralities during each memory access. A sense amplifier is configured to read the bit and nbit connections of the first and second pluralities via respectively the first and second multiplexers. The sense amplifier is designed to output a logic state from any of the cells based upon a voltage differential and a polarity between the bit and nbit connections of any of the columns. A write driver is configured to write the bit and nbit connections of the first and second plurality via respectively the first and second multiplexers. The write driver drives a logic state onto any of the cells based upon the voltage differential and the polarity between the bit and nbit connections of any of the columns.

摘要翻译： 改进的随机存取存储器（RAM）系统提高了速度并降低了与RAM相关联的功耗和逻辑复杂度。 RAM系统包括第一和第二多个RAM单元列。 每个列包括（1）至少一个RAM单元，每个RAM单元被配置为读取和写入相应的逻辑状态，以及（2）连接到每个RAM单元的位和n位连接（差分和互补）。 第一多路复用器被设计为复用第一多个RAM单元列的位和n位连接。 第二多路复用器被配置为复用第二多个列的位和n位连接。 解码逻辑控制第一和第二多路复用器，并且解码逻辑在每个存储器访问期间访问第一和第二多个之一中的特定列和单元。 读出放大器被配置为分别经由第一和第二多路复用器读取第一和第二多个的位和n位连接。 感测放大器被设计为基于任何列的电压差和位和n位连接之间的极性从任何单元输出逻辑状态。 写入驱动器被配置为分别写入第一和第二多个通道的位和n位连接分别为第一和第二多路复用器。 写入驱动器基于任何列的电压差和位和n位连接之间的极性将逻辑状态驱动到任何单元上。

公开(公告)号：US07430145B2

公开(公告)日：2008-09-30

申请号：US11229084

申请日：2005-09-16

申请人： Donald R. Weiss ,  John Wuu ,  Charles Morrganti

发明人： Donald R. Weiss ,  John Wuu ,  Charles Morrganti

IPC分类号： G11C7/00

CPC分类号： G11C29/42 ,  G06F11/1064 ,  G11C29/72

摘要： According to one embodiment, a method comprises detecting a defect in a portion of memory. The method further comprises designating the portion of memory as defective, and avoiding attempts to access the portion of memory designated as defective.

摘要翻译： 根据一个实施例，一种方法包括检测存储器的一部分中的缺陷。 该方法还包括将存储器的该部分指定为有缺陷的，并且避免尝试访问指定为有缺陷的存储器的部分。

公开(公告)号：US20130070513A1

公开(公告)日：2013-03-21

申请号：US13561547

申请日：2012-07-30

申请人： Donald R. Weiss ,  John J. Wuu

发明人： Donald R. Weiss ,  John J. Wuu

IPC分类号： G11C5/14

CPC分类号： G11C13/0002 ,  G11C5/005 ,  G11C11/4125 ,  G11C14/0045 ,  H03K19/0016 ,  H03K19/0019

摘要： An integrated circuit employs at least one active memory circuit and at least one memory state backup circuit wherein the at least one memory state backup circuit includes at least one passive variable resistance memory cell and at least one passive variable resistance memory cell interface that are used to backup data from the active memory circuit to the PVRM cell. Data is then placed back into the active memory circuit from the PVRM cell during a restore operation. The PVRM cell interface is operative to read the PVRM cell in response to a restore signal. PVRM cell interface control logic is operative to remove power to the PVRM cell after backup of the data to the PVRM cell from the active memory circuit. A PVRM cell (e.g., a bit cell) is added to each memory circuit that stores state information on an integrated circuit.

摘要翻译： 集成电路采用至少一个有源存储器电路和至少一个存储器状态备用电路，其中所述至少一个存储器状态备用电路包括至少一个可变电阻存储器单元和至少一个被动可变电阻存储单元接口， 备份数据从活动存储器电路到PVRM单元。 然后在还原操作期间将数据从PVRM单元放回到有源存储器电路中。 响应于恢复信号，PVRM单元接口可操作以读取PVRM单元。 PVRM单元接口控制逻辑用于在将数据从有源存储器电路备份到PVRM单元之后去除PVRM单元的电力。 将PVRM单元（例如，位单元）添加到在集成电路上存储状态信息的每个存储器电路。

公开(公告)号：US08276039B2

公开(公告)日：2012-09-25

申请号：US12394701

申请日：2009-02-27

申请人： John J. Wuu ,  Samuel D. Naffziger ,  Donald R. Weiss

发明人： John J. Wuu ,  Samuel D. Naffziger ,  Donald R. Weiss

IPC分类号： H03M13/00

CPC分类号： H03M13/2927 ,  G06F11/1064 ,  H03M13/2906 ,  H03M13/2909

摘要： A first error detection for a first data word is performed using a first error correction code associated with the first data word. In response to the first error detection indicating a first uncorrectable error at the first data word based upon the first error correction code, a second error detection for a plurality of data words including the first data word and a second data word is performed using a second error correction code based upon the first and second data words.

摘要翻译： 使用与第一数据字相关联的第一纠错码来执行第一数据字的第一错误检测。 响应于基于第一纠错码在第一数据字处指示第一不可校正错误的第一错误检测，使用第二错误检测来执行包括第一数据字和第二数据字的多个数据字的第二错误检测 基于第一和第二数据字的纠错码。

公开(公告)号：US20100301482A1

公开(公告)日：2010-12-02

申请号：US12475989

申请日：2009-06-01

申请人： Richard T. Schultz ,  Donald R. Weiss

发明人： Richard T. Schultz ,  Donald R. Weiss

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76895 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

摘要： Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodiments include forming a gate hard mask over gates, forming bidirectional trenches overlying portions of the gate electrodes and active silicon regions, etching the hard mask layer to expose regions of the gate electrodes that are to connect to local interconnects, and filling the trenches with conductive material to form self-aligned local interconnects.

摘要翻译： 通过提供双向，自对准局部互连的技术，通过在未连接到局部互连的栅极的部分上采用栅极硬掩模，技术来形成改进的SRAM，从而显着减少与栅极短路的局部互连。 实施例包括在栅极上形成栅极硬掩模，形成覆盖栅极电极和有源硅区域的部分的双向沟槽，蚀刻硬掩模层以暴露栅极电极连接到局部互连的区域，以及用导电 材料以形成自对准局部互连。

公开(公告)号：US07724578B2

公开(公告)日：2010-05-25

申请号：US11639865

申请日：2006-12-15

申请人： Michael A. Dreesen ,  John J. Wuu ,  Donald R. Weiss

发明人： Michael A. Dreesen ,  John J. Wuu ,  Donald R. Weiss

IPC分类号： G11C16/06

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C11/404 ,  G11C11/4091 ,  G11C2207/063 ,  G11C2211/4016

摘要： A memory device includes a memory array and a sense amplifier. The memory array includes a floating body cell configured to store a bit value. The sense amplifier includes a bit output configured to provide an output voltage representative of the bit value and a reference source configured to provide a reference voltage. The sense amplifier further includes a current mirror configured to provide a current to the first floating body cell based on the reference voltage, and a differential amplifier circuit configured to determine the output voltage based on the reference voltage and a voltage across the floating body cell resulting from application of the current to the floating body cell.

摘要翻译： 存储器件包括存储器阵列和读出放大器。 存储器阵列包括被配置为存储位值的浮体单元。 感测放大器包括被配置为提供表示比特值的输出电压的位输出和被配置为提供参考电压的参考源。 感测放大器还包括电流镜，其被配置为基于参考电压向第一浮动体单元提供电流;以及差分放大器电路，其被配置为基于参考电压和浮体电池两端的电压来确定输出电压 从电流应用到浮体细胞。

公开(公告)号：US20120037996A1

公开(公告)日：2012-02-16

申请号：US13280848

申请日：2011-10-25

申请人： Richard T. Schultz ,  Donald R. Weiss

发明人： Richard T. Schultz ,  Donald R. Weiss

IPC分类号： H01L27/11

CPC分类号： H01L21/76895 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

摘要： Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodiments include forming a gate hard mask over gates, forming bidirectional trenches overlying portions of the gate electrodes and active silicon regions, etching the hard mask layer to expose regions of the gate electrodes that are to connect to local interconnects, and filling the trenches with conductive material to form self-aligned local interconnects.

摘要翻译： 通过提供双向，自对准局部互连的技术，通过在未连接到局部互连的栅极的部分上采用栅极硬掩模，技术来形成改进的SRAM，从而显着减少与栅极短路的局部互连。 实施例包括在栅极上形成栅极硬掩模，形成覆盖栅极电极和有源硅区域的部分的双向沟槽，蚀刻硬掩模层以暴露栅极电极连接到局部互连的区域，以及用导电 材料以形成自对准局部互连。