公开(公告)号：US20130229860A1

公开(公告)日：2013-09-05

申请号：US13865279

申请日：2013-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

公开(公告)号：US20140353740A1

公开(公告)日：2014-12-04

申请号：US14283245

申请日：2014-05-21

Applicant: Renesas Electronics Corporation

Inventor： Akio Nishida ,  Kota Funayama

IPC: H01L27/115 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/823864 ,  H01L27/11573 ,  H01L27/1207 ,  H01L29/66833

Abstract: Improvements are achieved in the characteristics of a semiconductor device having a nonvolatile memory (MONOS). In a SOI substrate having a supporting substrate, an insulating layer formed thereover, and a silicon layer formed thereover, the MONOS is formed. The MONOS has a control gate electrode and a memory gate electrode formed so as to be adjacent to the control gate electrode above the semiconductor layer. The MONOS also has a first impurity region formed in the supporting substrate under the control gate electrode and a second impurity region formed in the supporting substrate under the memory gate electrode and having an effective carrier concentration lower than that of the first impurity region. By thus providing the first and second impurity regions for adjusting the respective thresholds of the control transistor and the memory transistor, variations in the thresholds of the individual transistors are reduced to reduce GiDL.

Abstract translation: 具有非易失性存储器（MONOS）的半导体器件的特性得到改善。 在具有支撑基板的SOI基板中，形成有绝缘层，形成有硅层，形成MONOS。 MONOS具有形成为与半导体层上方的控制栅电极相邻的控制栅电极和存储栅电极。 MONOS还具有形成在支撑衬底下的第一杂质区域，在控制栅电极下方形成第二杂质区域，以及形成在存储栅电极下方的支撑衬底中并具有比第一杂质区域低的有效载流子浓度的第二杂质区域。 通过提供用于调节控制晶体管和存储晶体管的相应阈值的第一和第二杂质区域，各个晶体管的阈值的变化被减小以减少GiDL。