公开(公告)号：US20060179249A1

公开(公告)日：2006-08-10

申请号：US11055697

申请日：2005-02-10

申请人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Phillip Williams

发明人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Phillip Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0813

摘要： A cache coherent data processing system includes a memory and at least first and second coherency domains that each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation targeting a request address allocated to the memory from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains. The master selects the scope based, at least in part, upon whether the memory belongs to the first coherency domain and performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.

摘要翻译： 高速缓存一致数据处理系统包括存储器和至少第一和第二一致性域，每个域包括第一和第二高速缓存存储器中的相应一个。 第一相干域中的主机从仅包括第一相关域的第一范围和包括第一和第二相干域的第二范围中选择针对分配给存储器的请求地址的操作的初始广播的范围。 主设备至少部分地基于所述存储器是否属于第一相关域并且使用所选择的范围来执行在高速缓存相干数据处理系统内的操作的初始广播来选择所述范围。

公开(公告)号：US20060176890A1

公开(公告)日：2006-08-10

申请号：US11055467

申请日：2005-02-10

申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke

发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke

IPC分类号： H04L12/56 ,  H04L12/28

CPC分类号： G06F15/16

摘要： A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts operations received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units.

摘要翻译： 数据处理系统包括多个处理单元，每个处理单元各自具有与多个处理单元中的多个其他处理单元中的每一个相对的点对点通信链路，但是比所有多个处理单元少。 多个处理单元中的每一个包括互连逻辑，耦合到该处理单元的每个点对点通信链路，其将从多个处理单元中的多个其中一个处理单元接收的操作广播到多个处理单元中的一个或多个 处理单位。

公开(公告)号：US20060119397A1

公开(公告)日：2006-06-08

申请号：US11002548

申请日：2004-12-02

申请人： Frank Ferraiolo ,  James Fields ,  Norman James ,  Bradley McCredie

发明人： Frank Ferraiolo ,  James Fields ,  Norman James ,  Bradley McCredie

IPC分类号： G01R29/02

CPC分类号： G01R31/31725

摘要： An apparatus and method for accurately tuning the speed of an integrated circuit, i.e. a computer chip, using a built-in sense circuit and controller are provided. The sense circuit is provided in association with a monitored path. The sense circuit includes a variable delay element coupled to a controller. A data signal from the monitored path is provided to the sense circuit which adds an amount of delay as determined by the controller to the data signal. The delayed data signal and the original data signal are compared to determine if their values match. If they match, then the amount of delay added by the variable delay element is increased. If they do not match, then a previous amount of delay, prior to the mismatch, is output as the slack of the monitored path. The slack may then be used to tune the speed of the integrated circuit.

公开(公告)号：US20070226426A1

公开(公告)日：2007-09-27

申请号：US11388016

申请日：2006-03-23

申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831

摘要： A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain includes a system memory controller for a system memory and a first processing unit having a first cache memory. The second coherency domain includes a second processing unit having a second cache memory. In the first cache memory, a coherency state field associated with a storage location and an address tag is set to a first coherency state. In response to snooping an exclusive access request specifying a target address matching the address tag, the first cache memory provides a first partial response to the exclusive access request based at least in part upon the first coherency state. In response to snooping the exclusive access request, the memory controller determines whether it is responsible for the target address and provides a second partial response to the exclusive access request based at least in part upon an outcome of the determination. At least the first and second partial responses are accumulated to obtain a combined response for the exclusive access request. The combined response includes an indication of whether or not a highest point of coherency and a memory controller of a home system memory for the target address reside within a same coherency domain. The first cache memory updates the coherency state field from the first coherency state to a second coherency state in response to the indication in the combined response.

摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 第一相干域包括用于系统存储器的系统存储器控制器和具有第一高速缓冲存储器的第一处理单元。 第二相关域包括具有第二高速缓冲存储器的第二处理单元。 在第一缓存存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为第一相关性状态。 响应于窥探专用访问请求，指定与地址标签匹配的目标地址，第一高速缓存存储器至少部分地基于第一相关性状态向独占访问请求提供第一部分响应。 响应于窥探专用访问请求，存储器控制器至少部分地基于确定的结果来确定它是否对目标地址负责并且向独占访问请求提供第二部分响应。 至少第一和第二部分响应被累积以获得专用访问请求的组合响应。 组合响应包括关于目标地址的家庭系统存储器的最高点的一致性和存储器控制器是否位于相同的一致性域内的指示。 响应于组合响应中的指示，第一缓存存储器将相关性状态字段从第一相关性状态更新为第二相关性状态。

公开(公告)号：US20070073501A1

公开(公告)日：2007-03-29

申请号：US11236449

申请日：2005-09-27

申请人： Andreas Bieswanger ,  Herwig Elfering ,  James Fields ,  Andrew Geissler ,  Alan Hlava ,  Scott Swaney

发明人： Andreas Bieswanger ,  Herwig Elfering ,  James Fields ,  Andrew Geissler ,  Alan Hlava ,  Scott Swaney

IPC分类号： G01N37/00

CPC分类号： G01R31/2894

摘要： A computer implemented method, a data processing system, and a computer usable program code for automatically identifying multiple combinations of operational and non-operational components with a single part number. A non-volatile storage is provided on a part, wherein the part includes a plurality of sub-components. Unavailable sub-components in the plurality of sub-components are identified based on a series of testing to form identified unavailable sub-components. Information of the identified unavailable sub-components is stored into the non-volatile storage.

摘要翻译： 计算机实现的方法，数据处理系统和用于使用单个部件号自动识别操作和非操作部件的多个组合的计算机可用程序代码。 在部件上提供非易失性存储器，其中该部件包括多个子部件。 基于一系列测试来识别多个子组件中不可用的子组件，以形成所识别的不可用子组件。 所识别的不可用子组件的信息被存储到非易失性存储器中。

公开(公告)号：US20060184742A1

公开(公告)日：2006-08-17

申请号：US11056649

申请日：2005-02-12

申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  Bradley McCredie ,  William Starke

发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  Bradley McCredie ,  William Starke

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/127

摘要： A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.

摘要翻译： 一种用于实现跨层级高速缓冲存储器的干预的方法，系统和设备。 在优选实施例中，响应于第一高速缓冲存储器中的高速缓存未命中，直接干预请求从第一高速缓存存储器发送到第二高速缓存存储器，请求满足高速缓存未命中的直接干预。 在替代实施例中，利用直接干预来访问相同级别的受害者缓存。

公开(公告)号：US20060179245A1

公开(公告)日：2006-08-10

申请号：US11055476

申请日：2005-02-10

申请人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F12/084

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

公开(公告)号：US20060179241A1

公开(公告)日：2006-08-10

申请号：US11054886

申请日：2005-02-10

申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke

发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke

IPC分类号： G06F13/28

CPC分类号： G06F12/0844 ,  G06F12/0817 ,  G06F12/0831

摘要： A cache coherent data processing system includes at least first and second coherency domains coupled for communication. The first and second coherency domains each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains based, at least in part, upon a type of the operation. The master then performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.

摘要翻译： 高速缓存一致数据处理系统至少包括耦合用于通信的第一和第二相干域。 第一和第二相关域各自包括第一和第二高速缓存存储器中的相应一个。 第一相关域中的主机至少部分地基于类型，从包括第一相关域的第一范围和包括第一和第二相干域两者的第二范围中选择操作的初始广播的范围 的操作。 然后，主机使用所选择的范围在高速缓存相干数据处理系统内执行操作的初始广播。

公开(公告)号：US20060179237A1

公开(公告)日：2006-08-10

申请号：US11054173

申请日：2005-02-09

申请人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  Jeffrey Stuecheli

发明人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  Jeffrey Stuecheli

IPC分类号： G06F13/28 ,  G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0851

摘要： A method and apparatus for performing data prefetch in a multiprocessor system are disclosed. The multiprocessor system includes multiple processors, each having a cache memory. The cache memory is subdivided into multiple slices. A group of prefetch requests is initially issued by a requesting processor in the multiprocessor system. Each prefetch request is intended for one of the respective slices of the cache memory of the requesting processor. In response to the prefetch requests being missed in the cache memory of the requesting processor, the prefetch requests are merged into one combined prefetch request. The combined prefetch request is then sent to the cache memories of all the non-requesting processors within the multiprocessor system. In response to a combined clean response from the cache memories of all the non-requesting processors, data are then obtained for the combined prefetch request from a system memory.

摘要翻译： 公开了一种用于在多处理器系统中执行数据预取的方法和装置。 多处理器系统包括多个处理器，每个具有高速缓冲存储器。 缓存存储器被细分成多个片段。 一组预取请求最初由多处理器系统中的请求处理器发出。 每个预取请求用于请求处理器的高速缓冲存储器的相应片段之一。 响应于在请求处理器的高速缓冲存储器中错过的预取请求，预取请求被合并成一个组合预取请求。 然后将组合的预取请求发送到多处理器系统内的所有不请求处理器的高速缓冲存储器。 响应于来自所有非请求处理器的高速缓冲存储器的组合清洁响应，然后从系统存储器获得用于组合预取请求的数据。

公开(公告)号：US10207462B1

公开(公告)日：2019-02-19

申请号：US14641365

申请日：2015-03-07

申请人： James Fields ,  Michael Manhardt

发明人： James Fields ,  Michael Manhardt ,  Benjamin Malouf

IPC分类号： B29C67/00 ,  B29C64/321 ,  B65H51/10 ,  B65H57/14 ,  B29C64/118

摘要： A material transport assembly for a printer assembly can include a toothed component; a drive for rotation of the toothed component; a material guide; and a biasing component that biases the material guide in a direction toward the toothed component.