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    Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memory
    1.
    发明申请
    Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memory 有权
    数据处理系统和方法，用于使用存储器的位置预测性地选择操作的广播范围

    公开(公告)号：US20060179249A1

    公开(公告)日：2006-08-10

    申请号：US11055697

    申请日：2005-02-10

    申请人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Phillip Williams

    发明人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Phillip Williams

    IPC分类号： G06F13/28

    CPC分类号： G06F12/0831 ,  G06F12/0813

    摘要： A cache coherent data processing system includes a memory and at least first and second coherency domains that each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation targeting a request address allocated to the memory from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains. The master selects the scope based, at least in part, upon whether the memory belongs to the first coherency domain and performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.

    摘要翻译： 高速缓存一致数据处理系统包括存储器和至少第一和第二一致性域，每个域包括第一和第二高速缓存存储器中的相应一个。 第一相干域中的主机从仅包括第一相关域的第一范围和包括第一和第二相干域的第二范围中选择针对分配给存储器的请求地址的操作的初始广播的范围。 主设备至少部分地基于所述存储器是否属于第一相关域并且使用所选择的范围来执行在高速缓存相干数据处理系统内的操作的初始广播来选择所述范围。

    Reducing number of rejected snoop requests by extending time to respond to snoop request
    3.
    发明申请
    Reducing number of rejected snoop requests by extending time to respond to snoop request 失效

    公开(公告)号：US20060184748A1

    公开(公告)日：2006-08-17

    申请号：US11056740

    申请日：2005-02-11

    申请人： Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

    发明人： Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

    IPC分类号： G06F13/28

    CPC分类号： G06F12/0831

    摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.

    Reducing Number of Rejected Snoop Requests By Extending Time to Respond to Snoop Request
    4.
    发明申请
    Reducing Number of Rejected Snoop Requests By Extending Time to Respond to Snoop Request 失效
    通过延长响应Snoop请求的时间来减少被拒绝的侦听请求数

    公开(公告)号：US20070294486A1

    公开(公告)日：2007-12-20

    申请号：US11847941

    申请日：2007-08-30

    申请人： Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

    发明人： Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0831

    摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.

    摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 缓存中的“停止/重新排序单元”从互连中接收窥探请求。 窥探请求的诸如地址的信息被存储在失速/重新排序单元的队列中。 停止/重新排序单元将窥探请求转发到也从处理器接收请求的选择器。 仲裁机制选择来自处理器的窥探请求或请求。 如果侦听请求被仲裁机制拒绝，关于窥探请求的信息（例如地址）可以被保留在停止/重新排序单元中。 请求可能会稍后重新发送到选择器。 该过程可以重复直到“n”个时钟周期。 通过提供窥探请求仲裁机制接受的额外机会（n个时钟周期），最终可能会拒绝更少的侦听请求。

    Reducing Number of Rejected Snoop Requests By Extending Time To Respond To Snoop Request
    6.
    发明申请
    Reducing Number of Rejected Snoop Requests By Extending Time To Respond To Snoop Request 失效
    通过延长响应Snoop请求的时间减少被拒绝的侦听请求数

    公开(公告)号：US20080077744A1

    公开(公告)日：2008-03-27

    申请号：US11950717

    申请日：2007-12-05

    申请人： Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

    发明人： Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

    IPC分类号： G06F13/28

    CPC分类号： G06F12/0831

    摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.

    摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 缓存中的“停止/重新排序单元”从互连中接收窥探请求。 窥探请求的诸如地址的信息被存储在失速/重新排序单元的队列中。 停止/重新排序单元将窥探请求转发到也从处理器接收请求的选择器。 仲裁机制选择来自处理器的窥探请求或请求。 如果侦听请求被仲裁机制拒绝，关于窥探请求的信息（例如地址）可以被保留在停止/重新排序单元中。 请求可能会稍后重新发送到选择器。 该过程可以重复直到“n”个时钟周期。 通过提供窥探请求仲裁机制接受的额外机会（n个时钟周期），最终可能会拒绝更少的侦听请求。

    Data processing system, method and interconnect fabric for synchronized communication in a data processing system
    7.
    发明申请
    Data processing system, method and interconnect fabric for synchronized communication in a data processing system 失效
    数据处理系统，方法和互连结构，用于数据处理系统中的同步通信

    公开(公告)号：US20060179337A1

    公开(公告)日：2006-08-10

    申请号：US11055299

    申请日：2005-02-10

    申请人： Benjiman Goodman ,  Guy Guthrie ,  Praveen Reddy ,  William Starke ,  Jeffrey Stuecheli

    发明人： Benjiman Goodman ,  Guy Guthrie ,  Praveen Reddy ,  William Starke ,  Jeffrey Stuecheli

    IPC分类号： G06F1/04 ,  G06F1/12 ,  G06F15/16

    CPC分类号： G06F15/16

    摘要： A data processing system includes a plurality of processing units, including at least a local master and a local hub, which are coupled for communication via a communication link. The local master includes a master capable of initiating an operation, a snooper capable of receiving an operation, and interconnect logic coupled to a communication link coupling the local master to the local hub. The interconnect logic includes request logic that synchronizes internal transmission of a request of the master to the snooper with transmission, via the communication link, of the request to the local hub.

    摘要翻译： 数据处理系统包括多个处理单元，至少包括本地主站和本地集线器，其经由通信链路进行通信。 本地主机包括能够启动操作的主机，能够接收操作的监听器，以及耦合到将本地主机耦合到本地集线器的通信链路的逻辑互连。 互连逻辑包括请求逻辑，其将主机的请求的内部传输与通过通信链路传送到本地集线器的请求同步到窥探者的请求逻辑。

    DATA PROCESSING SYSTEM AND METHOD OF DATA PROCESSING SUPPORTING TICKET-BASED OPERATION TRACKING
    8.
    发明申请
    DATA PROCESSING SYSTEM AND METHOD OF DATA PROCESSING SUPPORTING TICKET-BASED OPERATION TRACKING 审中-公开
    数据处理系统和数据处理方法支持基于票单的操作跟踪

    公开(公告)号：US20070266126A1

    公开(公告)日：2007-11-15

    申请号：US11279643

    申请日：2006-04-13

    申请人： Leo Clark ,  James Fields ,  Benjiman Goodman ,  William Starke ,  Jeffrey Stuecheli

    发明人： Leo Clark ,  James Fields ,  Benjiman Goodman ,  William Starke ,  Jeffrey Stuecheli

    IPC分类号： G06F15/173

    CPC分类号： G06F12/0831 ,  G06F12/0897 ,  G06F12/1458

    摘要： A data processing system includes a plurality of processing units coupled by a plurality of communication links for point-to-point communication such that at least some of the communication between multiple different ones of the processing units is transmitted via intermediate processing units among the plurality of processing units. The communication includes operations having a request and a combined response representing a system response to the request. At least each intermediate processing unit includes one or more masters that initiate first operations, a snooper that receives at least second operations initiated by at least one other of the plurality of processing units, a physical queue that stores master tags of first operations initiated by the one or more masters within that processing unit, and a ticketing mechanism that assigns to second operations observed at the intermediate processing unit a ticket number indicating an order of observation with respect to other second operations observed by the intermediate processing unit. The ticketing mechanism provides the ticket number assigned to an operation to the snooper for processing with a combined response of the operation.

    摘要翻译： 数据处理系统包括由多个通信链路耦合用于点对点通信的多个处理单元，使得多个处理单元中的多个不同处理单元之间的通信中的至少一些通过多个处理单元之间的中间处理单元发送 处理单位。 该通信包括具有请求的操作和表示对请求的系统响应的组合响应。 至少每个中间处理单元包括启动第一操作的一个或多个主机，至少接收由所述多个处理单元中的至少另一个处理单元发起的至少第二操作的侦听器;存储由所述多个处理单元发起的第一操作的主标签的物理队列 在该处理单元内的一个或多个主设备，以及票据机构，其分配在中间处理单元处观察到的第二操作，该票单号指示关于由中间处理单元观察到的其他第二操作的观察次序。 票务机制将分配给操作员的操作的票号提供给操作的组合响应进行处理。

    Data processing system and method for efficient communication utilizing an Tn and Ten coherency states
    9.
    发明申请
    Data processing system and method for efficient communication utilizing an Tn and Ten coherency states 有权
    数据处理系统和利用Tn和10相​​关性状态的高效通信方法

    公开(公告)号：US20080040556A1

    公开(公告)日：2008-02-14

    申请号：US11835984

    申请日：2007-08-08

    申请人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Derek Williams

    发明人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Derek Williams

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F12/084

    摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

    摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。 第一相关域包括第一高速缓存存储器和第二高速缓冲存储器，并且第二相干域包括远程一致高速缓存存储器。 第一高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。 缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。 相关性状态字段具有多个可能的状态，包括指示存储器块可能与第一相关域中的第二高速缓冲存储器共享并且仅在第一相干域内缓存的状态。