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    Programmable logic array having local and long distance conductors
    11.
    发明授权
    Programmable logic array having local and long distance conductors 失效
    具有本地和长距离导体的可编程逻辑阵列

    公开(公告)号：US5260611A

    公开(公告)日：1993-11-09

    申请号：US880942

    申请日：1992-05-08

    申请人： Richard G. Cliff ,  Bahram Ahanin ,  Craig S. Lytle ,  Francis B. Heile ,  Bruce B. Pedersen ,  Kerry Veenstra

    发明人： Richard G. Cliff ,  Bahram Ahanin ,  Craig S. Lytle ,  Francis B. Heile ,  Bruce B. Pedersen ,  Kerry Veenstra

    IPC分类号： H01L21/82 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17792

    摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit.

    摘要翻译： 可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。 提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。 此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的 网络。 提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。

    PCI-compatible programmable logic devices
    12.
    发明授权
    PCI-compatible programmable logic devices 有权
    PCI兼容的可编程逻辑器件

    公开(公告)号：US06646467B1

    公开(公告)日：2003-11-11

    申请号：US10147200

    申请日：2002-05-17

    申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pendersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

    发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pendersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

    IPC分类号： H03K19177

    CPC分类号： H03K19/1774 ,  H03K19/17744

    摘要： A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Some of the registers on the device are closely coupled for data input and output to data signal input/output pins of the device. The clock signal input terminals of at least these registers are also closely coupled to the clock signal input pin of the device. Programmable input delay is provided between the data signal input/output pins and the data input terminals of the above-mentioned registers to help compensate for clock signal skew on the device.

    摘要翻译： 可编程逻辑集成电路器件具有几个功能，可帮助其根据PCI特殊兴趣组的外设组件接口（“PCI”）信令协议执行。 设备上的一些寄存器紧密耦合，用于数据输入和输出到器件的数据信号输入/输出引脚。 至少这些寄存器的时钟信号输入端也紧密耦合到器件的时钟信号输入引脚。 在数据信号输入/输出引脚和上述寄存器的数据输入端之间提供可编程输入延迟，以帮助补偿器件上的时钟信号偏移。

    Programmable logic device with highly routable interconnect
    20.
    发明授权
    Programmable logic device with highly routable interconnect 失效
    具有高度可路由互连的可编程逻辑器件

    公开(公告)号：US06294928B1

    公开(公告)日：2001-09-25

    申请号：US08838398

    申请日：1997-04-03

    申请人： Craig S. Lytle ,  Kerry S. Veenstra ,  Francis B. Heile

    发明人： Craig S. Lytle ,  Kerry S. Veenstra ,  Francis B. Heile

    IPC分类号： H01L2500

    CPC分类号： H03K19/17736 ,  H03K19/177 ,  H03K19/17728

    摘要： A programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs), programmable interconnect structure, and other logical elements forms a Clos network. After specific constraints have been met, the architecture is guaranteed to route. The architecture is provably routable when there is no fan-out in the middle stage. A LAB (A-200) comprises an input multiplexer region (A-504), logic elements (A-300), input-output pins (A-516), and output multiplexer region (A-508). Furthermore, a logic device and a method of operating a logic device. The device includes logic elements (B-240) that perform desired logic functions and routing functions. The logic elements (B-240) are arranged in larger logic blocks known as logic array blocks (B-230) that have local interconnection systems. The logic array blocks (B-230) are configured to provide global interconnections. The configuration provides a Clos network, whereby a signal may be routed from any input to any output without blocking.

    摘要翻译： 具有高可路由可编程互连结构的可编程逻辑器件架构。 逻辑阵列块（LAB），可编程互连结构和其他逻辑元件的布置形成了Clos网络。 在满足特定约束之后，保证架构的路由。 当中间阶段没有扇出的时候，这个架构是可行的。 AAB（A-200）包括输入多路复用器区域（A-504），逻辑元件（A-300），输入输出引脚（A-516）和输出多路复用器区域（A-508）。 此外，逻辑设备和操作逻辑设备的方法。 该设备包括执行所需逻辑功能和路由功能的逻辑元件（B-240）。 逻辑元件（B-240）被布置在具有本地互连系统的被称为逻辑阵列块（B-230）的较大逻辑块中。 逻辑阵列块（B-230）被配置为提供全局互连。 该配置提供了一个Clos网络，从而信号可以从任何输入路由到任何输出而不阻塞。