公开(公告)号：US07082055B2

公开(公告)日：2006-07-25

申请号：US11108634

申请日：2005-04-19

申请人： Masayuki Ichige ,  Riichiro Shirota ,  Kikuko Sugimae

发明人： Masayuki Ichige ,  Riichiro Shirota ,  Kikuko Sugimae

IPC分类号： G11C16/04

CPC分类号： H01L27/11521 ,  G11C16/04 ,  G11C16/0433 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524

摘要： A semiconductor integrated circuit device includes a semiconductor substrate, an element isolation region, a first interconnection, a second interconnection, and a memory cell unit connected between a corresponding one of the first interconnection and a second interconnection. The memory cell unit includes two selection transistors and memory cell transistors of not larger than two. The memory cell transistors are connected between the two selection transistors. The memory cell transistor has a charge storage layer whose side surface lies in the same plane or in substantially the same plane as the side surface of the element isolation regions.

公开(公告)号：US20060071293A1

公开(公告)日：2006-04-06

申请号：US11283742

申请日：2005-11-22

申请人： Masayuki Ichige ,  Riichiro Shirota ,  Yuji Takeuchi ,  Kikuko Sugimae

发明人： Masayuki Ichige ,  Riichiro Shirota ,  Yuji Takeuchi ,  Kikuko Sugimae

IPC分类号： H01L29/00

CPC分类号： H01L27/11526 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11541 ,  H01L27/11543

摘要： An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed therebetween. A second conductive layer is formed on the first conductive layer to extend into the element isolating region. A surface of that section of the second conductive layer which is positioned within the element isolating region is exposed, and a third conductive layer is formed on the second conductive layer with a second insulating film interposed therebetween. Further, a contact is electrically connected to an exposed surface of the second conductive layer.

公开(公告)号：US20050224894A1

公开(公告)日：2005-10-13

申请号：US11108634

申请日：2005-04-19

申请人： Masayuki Ichige ,  Riichiro Shirota ,  Kikuko Sugimae

发明人： Masayuki Ichige ,  Riichiro Shirota ,  Kikuko Sugimae

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/94

CPC分类号： H01L27/11521 ,  G11C16/04 ,  G11C16/0433 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524

摘要： A semiconductor integrated circuit device includes a semiconductor substrate, an element isolation region, a first interconnection, a second interconnection, and a memory cell unit connected between a corresponding one of the first interconnection and a second interconnection. The memory cell unit includes two selection transistors and memory cell transistors of not larger than two. The memory cell transistors are connected between the two selection transistors. The memory cell transistor has a charge storage layer whose side surface lies in the same plane or in substantially the same plane as the side surface of the element isolation regions.

摘要翻译： 半导体集成电路器件包括半导体衬底，元件隔离区，第一互连，第二互连和连接在第一互连和第二互连中的相应一个之间的存储单元单元。 存储单元单元包括不大于2的选择晶体管和存储单元晶体管。 存储单元晶体管连接在两个选择晶体管之间。 存储单元晶体管具有电荷存储层，该电荷存储层的侧表面位于与元件隔离区的侧表面相同的平面或基本上相同的平面中。

公开(公告)号：US07504294B2

公开(公告)日：2009-03-17

申请号：US10881180

申请日：2004-07-01

申请人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

发明人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

IPC分类号： H01L21/8238

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

摘要翻译： 半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫 在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能 仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

公开(公告)号：US07417281B2

公开(公告)日：2008-08-26

申请号：US11733488

申请日：2007-04-10

申请人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

发明人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

IPC分类号： H01L29/94

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

摘要翻译： 半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫 在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能 仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

公开(公告)号：US07067872B2

公开(公告)日：2006-06-27

申请号：US10891133

申请日：2004-07-15

申请人： Masayuki Ichige ,  Kikuko Sugimae ,  Riichiro Shirota

发明人： Masayuki Ichige ,  Kikuko Sugimae ,  Riichiro Shirota

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11546

摘要： A semiconductor memory device provided with a memory cell region having first gate electrodes and a peripheral circuit region having second gate electrodes includes first gate electrodes arranged a first distance apart from each other on a semiconductor substrate, second gate electrodes arranged a second distance, which is larger than the first distance, apart from each other on the semiconductor substrate, first diffusion layers formed in the semiconductor substrate, the first diffusion layers sandwiching the first gate electrodes, second diffusion layers formed in the semiconductor substrate, the second diffusion layers sandwiching the second gate electrodes, a first insulating film formed on the first diffusion layer, second insulating films formed on the side surfaces of the second gate electrodes, first silicide films formed on the first gate electrodes, second silicide films formed on the second gate electrodes, and third silicide films formed on the second diffusion layers.

公开(公告)号：US06925008B2

公开(公告)日：2005-08-02

申请号：US10256102

申请日：2002-09-27

申请人： Masayuki Ichige ,  Riichiro Shirota ,  Kikuko Sugimae

发明人： Masayuki Ichige ,  Riichiro Shirota ,  Kikuko Sugimae

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  G11C16/04 ,  G11C16/0433 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524

摘要： A semiconductor integrated circuit device includes a semiconductor substrate, an element isolation region, a first interconnection, a second interconnection, and a memory cell unit connected between a corresponding one of the first interconnection and a second interconnection. The memory cell unit includes two selection transistors and memory cell transistors of not larger than two. The memory cell transistors are connected between the two selection transistors. The memory cell transistor has a charge storage layer whose side surface lies in the same plane as the side surface of the element isolation regions.

摘要翻译： 半导体集成电路器件包括半导体衬底，元件隔离区，第一互连，第二互连和连接在第一互连和第二互连中的相应一个之间的存储单元单元。 存储单元单元包括不大于2的选择晶体管和存储单元晶体管。 存储单元晶体管连接在两个选择晶体管之间。 存储单元晶体管具有电荷存储层，其电荷存储层的侧表面位于与元件隔离区域的侧表面相同的平面中。

公开(公告)号：US20070187749A1

公开(公告)日：2007-08-16

申请号：US11733488

申请日：2007-04-10

申请人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

发明人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

摘要翻译： 半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫 在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能 仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

公开(公告)号：US07151686B2

公开(公告)日：2006-12-19

申请号：US10944910

申请日：2004-09-21

申请人： Kikuko Sugimae ,  Takuya Futatsuyama ,  Riichiro Shirota ,  Masayuki Ichige

发明人： Kikuko Sugimae ,  Takuya Futatsuyama ,  Riichiro Shirota ,  Masayuki Ichige

IPC分类号： G11C17/00

CPC分类号： G11C8/12 ,  G11C8/10 ,  G11C16/08

摘要： A semiconductor memory device having: a cell array including bit lines, word lines and memory cells disposed at crossings thereof, plural memory cells being connected in series to constitute a NAND cell unit, plural blocks being arranged, each being constituted by plural NAND cell units arranged in the word line direction; and a row decoder configured to select a block, wherein the row decoder includes: transferring transistor arrays disposed in association with the blocks, in each of which transistors are arranged for transferring word line drive voltages; first decode portions disposed in association with the transferring transistor arrays, which are applied with boosted voltages to selectively drive the transferring transistor arrays; and second decode portions configured to select one of the blocks, each of which is disposed to be shared by adjacent two first decode portions.

摘要翻译： 一种半导体存储器件，具有：包括位线，字线和位于其交叉处的存储单元的单元阵列，多个存储单元串联连接以构成NAND单元单元，多个块被布置，每个由多个NAND单元单元 排列在字线方向; 以及配置为选择块的行解码器，其中所述行解码器包括：传送与所述块相关联地布置的晶体管阵列，其中每个晶体管布置用于传送字线驱动电压; 与传输晶体管阵列相关联地设置的第一解码部分，其被施加升压电压以选择性地驱动传输晶体管阵列; 以及第二解码部分，被配置为选择所述块之一，每个块被布置为由相邻的两个第一解码部分共享。

公开(公告)号：US07442985B2

公开(公告)日：2008-10-28

申请号：US11283742

申请日：2005-11-22

申请人： Masayuki Ichige ,  Riichiro Shirota ,  Yuji Takeuchi ,  Kikuko Sugimae

发明人： Masayuki Ichige ,  Riichiro Shirota ,  Yuji Takeuchi ,  Kikuko Sugimae

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11541 ,  H01L27/11543

摘要： An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed therebetween. A second conductive layer is formed on the first conductive layer to extend into the element isolating region. A surface of that section of the second conductive layer which is positioned within the element isolating region is exposed, and a third conductive layer is formed on the second conductive layer with a second insulating film interposed therebetween. Further, a contact is electrically connected to an exposed surface of the second conductive layer.

摘要翻译： 在半导体存储器件的外围电路部分中形成用于分离半导体层的元件区域的元件隔离区域，并且第一导电层形成有元件区域，其间插入有第一绝缘膜。 第二导电层形成在第一导电层上以延伸到元件隔离区域中。 位于元件隔离区域内的第二导电层的该部分的表面被暴露，并且在第二导电层上形成第三导电层，其间插入有第二绝缘膜。 此外，触点电连接到第二导电层的暴露表面。