公开(公告)号：US20100100682A1

公开(公告)日：2010-04-22

申请号：US12256002

申请日：2008-10-22

申请人： Guy L. Guthrie ,  Thomas L. Jeremiah ,  William L. McNeil ,  Piyush C. Patel ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： Guy L. Guthrie ,  Thomas L. Jeremiah ,  William L. McNeil ,  Piyush C. Patel ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0862 ,  G06F12/128 ,  G06F2212/1028 ,  Y02D10/13

摘要： A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core that specifies a non-modifying access to a target coherency granule, a determination is made whether the memory access request hits or misses in a directory of the lower level victim cache. In response to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state, the lower level victim cache provides the target coherency granule of the memory access request to the upper level cache. The lower level victim cache preserves the target coherency granule in the lower level victim cache in a shared coherence state if the memory access request is of a first type and invalidates the target coherency granule if the memory access request is of a second type.

摘要翻译： 数据处理系统包括具有相关联的高级缓存和较低级别的受害缓存的处理器核心。 响应于指定对目标一致性粒子的不修改访问的处理器核心的存储器访问请求，确定存储器访问请求是否在较低级别的受害缓存的目录中命中或丢失。 响应于确定存储器访问请求在数据有效的相干状态中击中较低级别的受害者高速缓存，则较低级别的受害者缓存将存储器访问请求的目标一致性颗粒提供给高级缓存。 如果存储器访问请求是第一类型，则较低级别的受害者缓存在共享相干状态下保留较低级别的受害者缓存中的目标一致性粒子，如果存储器访问请求是第二类型，则使目标一致性粒子无效。

公开(公告)号：US07536513B2

公开(公告)日：2009-05-19

申请号：US11095734

申请日：2005-03-31

申请人： Guy L. Guthrie ,  Aaron C. Sawdey ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： Guy L. Guthrie ,  Aaron C. Sawdey ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0815 ,  G06F12/0831

摘要： In response to a master receiving a memory access request indicating a target address, the master accesses a first cache directory of an upper level cache of a cache hierarchy. In response to the target address being associated in the first cache directory with an entry having a valid address tag and a first invalid coherency state, the master issues a request specifying the target address on an interconnect fabric without regard to a coherency state associated with the target address in a second cache directory of a lower level cache of the cache hierarchy. In response to the target address having a second invalid coherency state with respect to the first cache directory, the master issues a request specifying the target address on an interconnect fabric after determining a coherency state associated with the target address in the second cache directory of the lower level cache of the cache hierarchy.

摘要翻译： 响应于主机接收到指示目标地址的存储器访问请求，主机访问高速缓存层级的高级缓存的第一高速缓存目录。 响应于目标地址与具有有效地址标签的条目和第一无效一致性状态在第一高速缓存目录中相关联的目标地址，主机在不考虑与该互连结构相关联的一致性状态的情况下发布指定互连结构上的目标地址的请求 目标地址在缓存层次结构的较低级缓存的第二高速缓存目录中。 响应于相对于第一高速缓存目录具有第二无效一致性状态的目标地址，主机在确定与第二高速缓存目录中的目标地址相关联的一致性状态之后，在互连结构上发出指定目标地址的请求 缓存层次结构的较低级缓存。

公开(公告)号：US07512742B2

公开(公告)日：2009-03-31

申请号：US11333615

申请日：2006-01-17

申请人： Leo J. Clark ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

发明人： Leo J. Clark ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a memory block is held in a storage location associated with an address tag and a coherency state field. A determination is made if a home system memory assigned an address associated with the memory block is within the first coherency domain. If not, the coherency state field is set to a coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, the first coherency domain does not contain the home system memory, and that, following formation of the coherency state, the memory block is cached outside of the first coherency domain.

摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 在数据处理系统的第一相关域内的第一高速缓存存储器中，存储块被保存在与地址标签和一致性状态字段相关联的存储位置中。 如果分配了与存储器块相关联的地址的归属系统存储器在第一相关域内，则确定。 如果不是，则将一致性状态字段设置为指示地址标签有效的一致性状态，即存储位置不包含有效数据，第一相干域不包含家庭系统存储器，并且在形成 一致性状态下，内存块被缓存在第一个相干域之外。

公开(公告)号：US20080301377A1

公开(公告)日：2008-12-04

申请号：US12190766

申请日：2008-08-13

申请人： GUY L. GUTHRIE ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

发明人： GUY L. GUTHRIE ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F2212/507

摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping an exclusive access operation, the exclusive access request specifying a target address matching the address tag and indicating a relative domain location of a requestor that initiated the exclusive access operation, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and whether a target memory block associated with the address tag is cached within the first coherency domain upon successful completion of the exclusive access operation based upon the relative location of the requestor.

摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 在数据处理系统的第一相关域内的第一高速缓冲存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为指示地址标签有效的第一数据无效一致性状态， 存储位置不包含有效数据。 响应于窥探独占访问操作，所述专用访问请求指定与所述地址标签相匹配的目标地址并且指示发起所述独占访问操作的请求者的相对域位置，所述第一高速缓存存储器从所述第一数据更新所述一致性状态字段 - 无效的一致性状态到指示地址标签有效的第二数据无效一致性状态，存储位置不包含有效数据，以及与地址标签相关联的目标存储器块是否被缓存在第一相关域内 基于请求者的相对位置成功完成独占访问操作。

公开(公告)号：US07409481B2

公开(公告)日：2008-08-05

申请号：US11055405

申请日：2005-02-10

申请人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F13/42 ,  G06F13/00

CPC分类号： G06F15/16

摘要： A data processing system includes a plurality of communication links and a plurality of processing units including a local master processing unit. The local master processing unit includes interconnect logic that couples the processing unit to one or more of the plurality of communication links and an originating master coupled to the interconnect logic. The originating master originates an operation by issuing a write-type request on at least one of the one or more communication links, receives from a snooper in the data processing system a destination tag identifying a route to the snooper, and, responsive to receipt of the combined response and the destination tag, initiates a data transfer including a data payload and a data tag identifying the route provided within the destination tag.

摘要翻译： 数据处理系统包括多个通信链路和包括本地主处理单元的多个处理单元。 本地主处理单元包括将处理单元耦合到多个通信链路中的一个或多个以及耦合到互连逻辑的始发主机的互连逻辑。 始发主机通过在一个或多个通信链路中的至少一个发出写入请求来发起操作，从数据处理系统中的窥探者接收标识到窥探者的路由的目的地标签，并且响应于接收到 组合响应和目的地标签，发起包括数据有效载荷和标识目的地标签内提供的路由的数据标签的数据传输。

公开(公告)号：US07340568B2

公开(公告)日：2008-03-04

申请号：US11056740

申请日：2005-02-11

申请人： Benjiman L. Goodman ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

发明人： Benjiman L. Goodman ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.

摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 缓存中的“停止/重新排序单元”从互连中接收窥探请求。 窥探请求的诸如地址的信息被存储在失速/重新排序单元的队列中。 停止/重新排序单元将窥探请求转发到也从处理器接收请求的选择器。 仲裁机制选择来自处理器的窥探请求或请求。 如果侦听请求被仲裁机制拒绝，关于窥探请求的信息（例如地址）可以被保留在停止/重新排序单元中。 请求可能会稍后重新发送到选择器。 该过程可以重复直到“n”个时钟周期。 通过提供窥探请求仲裁机制接受的额外机会（n个时钟周期），最终可能会拒绝更少的侦听请求。

公开(公告)号：US09176876B2

公开(公告)日：2015-11-03

申请号：US13445646

申请日：2012-04-12

申请人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams ,  Thomas R. Puzak

发明人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams ,  Thomas R. Puzak

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0811 ,  G06F12/12

摘要： A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.

公开(公告)号：US08103791B2

公开(公告)日：2012-01-24

申请号：US12195130

申请日：2008-08-20

申请人： Benjiman L. Goodman ,  Guy L. Guthrie ,  Praveen S. Reddy ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： Benjiman L. Goodman ,  Guy L. Guthrie ,  Praveen S. Reddy ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F15/173 ,  G06F12/00 ,  G06F13/14 ,  G06F1/04 ,  G06F1/12

CPC分类号： G06F15/16

摘要： A data processing system includes a plurality of processing units, including at least a local master and a local hub, which are coupled for communication via a communication link. The local master includes a master capable of initiating an operation, a snooper capable of receiving an operation, and interconnect logic coupled to a communication link coupling the local master to the local hub. The interconnect logic includes request logic that synchronizes internal transmission of a request of the master to the snooper with transmission, via the communication link, of the request to the local hub.

摘要翻译： 数据处理系统包括多个处理单元，至少包括本地主站和本地集线器，其经由通信链路进行通信。 本地主机包括能够启动操作的主机，能够接收操作的监听器，以及耦合到将本地主机耦合到本地集线器的通信链路的逻辑互连。 互连逻辑包括请求逻辑，其将主机的请求的内部传输与通过通信链路传送到本地集线器的请求同步到窥探者的请求逻辑。

公开(公告)号：US07818511B2

公开(公告)日：2010-10-19

申请号：US11847941

申请日：2007-08-30

申请人： Benjiman L. Goodman ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

发明人： Benjiman L. Goodman ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.

摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 缓存中的“停止/重新排序单元”从互连中接收窥探请求。 窥探请求的诸如地址的信息被存储在失速/重新排序单元的队列中。 停止/重新排序单元将窥探请求转发到也从处理器接收请求的选择器。 仲裁机制选择来自处理器的窥探请求或请求。 如果侦听请求被仲裁机制拒绝，关于窥探请求的信息（例如地址）可以被保留在停止/重新排序单元中。 请求可能会稍后重新发送到选择器。 该过程可以重复直到“n”个时钟周期。 通过提供窥探请求仲裁机制接受的额外机会（n个时钟周期），最终可能会拒绝更少的侦听请求。

公开(公告)号：US07743218B2

公开(公告)日：2010-06-22

申请号：US12190766

申请日：2008-08-13

申请人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Willams

发明人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Willams

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  G06F2212/507

摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping an exclusive access operation, the exclusive access request specifying a target address matching the address tag and indicating a relative domain location of a requestor that initiated the exclusive access operation, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and whether a target memory block associated with the address tag is cached within the first coherency domain upon successful completion of the exclusive access operation based upon the relative location of the requestor.

摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 在数据处理系统的第一相关域内的第一高速缓冲存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为指示地址标签有效的第一数据无效一致性状态， 存储位置不包含有效数据。 响应于窥探独占访问操作，所述专用访问请求指定与所述地址标签相匹配的目标地址并且指示发起所述独占访问操作的请求者的相对域位置，所述第一高速缓存存储器从所述第一数据更新所述一致性状态字段 - 无效的一致性状态到指示地址标签有效的第二数据无效一致性状态，存储位置不包含有效数据，以及与地址标签相关联的目标存储器块是否被缓存在第一相关域内 基于请求者的相对位置成功完成独占访问操作。