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公开(公告)号：US06952821B2
公开(公告)日：2005-10-04
申请号：US10223224
申请日：2002-08-19
申请人： Robert S. Schreiber
发明人： Robert S. Schreiber
摘要： A system and method of automatically configuring memory in a data processing system, including the steps of: receiving source code containing a loop nest, wherein the loop nest includes data arrays with affine indexes; optimizing source code by relocating elements from a first array in memory to a second array in memory; and executing the optimized source code.
摘要翻译： 一种在数据处理系统中自动配置存储器的系统和方法，包括以下步骤：接收包含循环嵌套的源代码，其中循环嵌套包括具有仿射索引的数据阵列; 通过将元素从内存中的第一个数组重定位到存储器中的第二个数组来优化源代码; 并且执行优化的源代码。
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公开(公告)号：US06298471B1
公开(公告)日：2001-10-02
申请号：US09378295
申请日：1999-08-20
申请人： Robert S. Schreiber
发明人： Robert S. Schreiber
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： Methods and apparatus are described for optimizing interconnections between busses and function units and registers. The method includes identifying each bus in a plurality of busses and at least one hardware component to which each bus is assigned for a given operation. At least two bus assignments are identified for which different operations occur on the same hardware component. Hardware components are assigned for different operations occurring on the same hardware component to the same bus. The optimization process can be efficiently carried out using conventional algorithms for solving assignment problems. Use of these assignment problem algorithms provides an efficient and reliable way of optimizing the bus assignments.
摘要翻译： 描述了用于优化总线和功能单元和寄存器之间的互连的方法和装置。 该方法包括识别多个总线中的每个总线以及为给定操作分配了每个总线的至少一个硬件组件。 至少识别两个总线分配，在同一个硬件组件上进行不同的操作。 硬件组件被分配用于在相同硬件组件上发生到同一总线的不同操作。 可以使用常规算法来有效地执行优化过程，以解决分配问题。 使用这些分配问题算法提供了一种高效可靠的优化总线分配的方法。
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13.发明授权Computer-implemented method for role discovery and simplification in access control systems 有权计算机实现的访问控制系统角色发现和简化方法公开(公告)号：US09405922B2
公开(公告)日：2016-08-02
申请号：US12348832
申请日：2009-01-05
CPC分类号： G06F21/6218 , G06F21/604 , G06F2221/2141
摘要： A method includes selecting a first biclique role in a plurality of roles and finding all roles in the plurality that have a set of vertices of a second type that is a subset of a set of vertices of the second type in the first role; removing each of the subsets from the set of vertices of the second type corresponding to the first role; and reassigning the vertices of the first type to the roles such that original associations between the vertices of the first type and the vertices of the second type are maintained.
摘要翻译： 一种方法包括在多个角色中选择第一双角色角色，并且发现多个角色中的所有角色具有作为第一角色中第二类型的一组顶点的子集的第二类型的顶点集合; 从对应于第一角色的第二类型的顶点集合中去除每个子集; 并且将第一类型的顶点重新分配给角色，使得保持第一类型的顶点和第二类型的顶点之间的原始关联。
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14.发明授权Independently controllable and reconfigurable virtual memory devices in memory modules that are pin-compatible with standard memory modules 有权与标准内存模块引脚兼容的内存模块中的独立可控和可重新配置的虚拟内存设备公开(公告)号：US08924639B2
公开(公告)日：2014-12-30
申请号：US13058048
申请日：2008-08-08
CPC分类号： G11C5/04 , G06F12/06 , G06F12/0646 , G06F13/1684 , G06F2212/1028 , G11C8/12 , Y02D10/13 , Y02D10/14
摘要： Various embodiments of the present invention are directed multi-core memory modules. In one embodiment, a memory module (500) includes memory chips, and a demultiplexer register (502) electronically connected to each of the memory chips and a memory controller. The memory controller groups one or more of the memory chips into at least one virtual memory device in accordance with changing performance and/or energy efficiency needs. The demultiplexer register (502) is configured to receive a command indentifying one of the virtual memory devices and send the command to the memory chips of the identified virtual memory device. In certain embodiments, the memory chips can be dynamic random access memory chips.
摘要翻译： 本发明的各种实施例是多核存储器模块。 在一个实施例中，存储器模块（500）包括存储器芯片和电连接到每个存储器芯片的解复用器寄存器（502）和存储器控制器。 存储器控制器根据改变的性能和/或能量效率需求将一个或多个存储器芯片组合成至少一个虚拟存储器设备。 解复用器寄存器（502）被配置为接收识别虚拟存储器设备中的一个并且将命令发送到所识别的虚拟存储器设备的存储器芯片的命令。 在某些实施例中，存储器芯片可以是动态随机存取存储器芯片。
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公开(公告)号：US08214601B2
公开(公告)日：2012-07-03
申请号：US10909057
申请日：2004-07-30
申请人： Dale Morris , Robert S. Schreiber
发明人： Dale Morris , Robert S. Schreiber
CPC分类号： G06F12/0804 , G06F12/0891
摘要： The present invention provides a system with a cache that indicates which, if any, of its sections contain data having spent status. The invention also provides a method for identifying cache sections containing data having spent status and then purging without writing back to main memory a cache line having at least one section containing data having spent status. The invention further provides a program that specifies a cache-line section containing data that is to acquire “spent” status. “Spent” data, herein, is useless modified or unmodified data that was formerly at least potentially useful data when it was written to a cache. “Purging” encompasses both invalidating and overwriting.
摘要翻译： 本发明提供一种具有高速缓存的系统，其指示其部分（如果有的话）包含具有已用状态的数据。 本发明还提供了一种用于识别包含具有已用状态的数据的缓存部分的方法，然后在不向主存储器写入具有至少一个包含具有已用状态的数据的部分的高速缓存行的情况下进行清除。 本发明还提供一种程序，其指定包含要获取“已用”状态的数据的高速缓存线段。 这里的“耗费”数据是无用的修改或未修改的数据，以前在写入高速缓存时至少是潜在的有用数据。 “清除”包括无效和覆盖。
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16.发明申请Computer-Implemented Method for Obtaining a Minimum Biclique Cover in a Bipartite Dataset 有权计算机实现的双向数据集中获取最小双面覆盖的方法公开(公告)号：US20100175111A1
公开(公告)日：2010-07-08
申请号：US12350130
申请日：2009-01-07
CPC分类号： G06F17/10
摘要： A method includes providing a bipartite graph having vertices of a first type, vertices of a second type, and a plurality of edges, wherein each edge joins a vertex of the first type with a vertex of the second type. A unipartite edge dual graph is generated from the bipartite graph, and a minimum clique partition of the edge dual graph is recursively determined. A biclique is then created in the bipartite graph corresponding to each clique in the minimum clique partition of the edge dual graph.
摘要翻译： 一种方法包括提供具有第一类型的顶点，第二类型的顶点和多个边缘的二分图，其中每个边缘将第一类型的顶点与第二类型的顶点相连接。 从二分图生成一个单边缘双图，并递归地确定边缘双图的最小分区。 然后在对应于边缘双图的最小集团分区中的每个团体的二分图中创建双面。
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17.发明授权Method of compilation optimization using an N-dimensional template for relocated and replicated alignment of arrays in data-parallel programs for reduced data communication during execution 失效使用N维模板进行编译优化的方法，用于数据并行程序中数组的重定位和复制对齐，用于在执行期间进行减少的数据通信
公开(公告)号：US5475842A
公开(公告)日：1995-12-12
申请号：US104755
申请日：1993-08-11
CPC分类号： G06F8/453
摘要： When a data-parallel language like Fortran 90 is compiled for a distributed-memory machine, aggregate data objects (such as arrays) are distributed across the processor memories. The mapping determines the amount of residual communication needed to bring operands of parallel operations into alignment with each other. A common approach is to break the mapping into two stages: first, an alignment that maps all the objects to an abstract template, and then a distribution that maps the template to the processors. This disclosure deals with two facets of the problem of finding alignments that reduce residual communication; namely, alignments that vary in loops, and objects that permit of replicated alignments. It is shown that loop-dependent dynamic alignment is sometimes necessary for optimum performance, and algorithms are provided so that a compiler can determine good dynamic alignments for objects within "do" loops. Also situations are identified in which replicated alignment is either required by the program itself (via spread operations) or can be used to improve performance. An algorithm based on network flow is proposed for determing which objects to replicate so as to minimize the total amount of broadcast communication in replication.
摘要翻译： 当为分布式存储器机器编译Fortran 90的数据并行语言时，聚合数据对象（例如阵列）分布在处理器存储器中。 映射确定使并行操作的操作数彼此对准所需的剩余通信量。 一种常见的方法是将映射分为两个阶段：首先，将所有对象映射到抽象模板，然后将模板映射到处理器的分布。 本公开涉及寻找减少残余通信的对齐问题的两个方面; 即循环中不同的对齐，以及允许复制对齐的对象。 显示了循环相关的动态对齐有时是最佳性能所必需的，并且提供了算法，以便编译器可以确定“do”循环内对象的良好动态对齐。 还可以确定复制对齐是程序本身需要的（通过扩展操作）或可用于提高性能的情况。 提出了一种基于网络流的算法，用于确定要复制的对象，以便最小化复制中广播通信的总量。
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公开(公告)号：US08812886B2
公开(公告)日：2014-08-19
申请号：US13058067
申请日：2008-08-13
CPC分类号： G06F12/0215 , G06F1/3203 , G06F13/1694 , G06F2212/1028 , G11C5/04 , G11C7/20 , Y02D10/13 , Y02D10/152
摘要： Various embodiments of the present invention are directed to methods that enable a memory controller to choose a particular operation mode for virtual memory devices of a memory module based on dynamic program behavior. In one embodiment, a method for determining an operation mode for each virtual memory device of a memory module includes selecting a metric (1001) that provides a standard by which performance and/or energy efficiency of the memory module is optimized during execution of one or more applications on a multicore processor. For each virtual memory device (1005), the method also includes collecting usage information (1006) associated with the virtual memory device over a period of time, determining an operation mode (1007) for the virtual memory device based on the metric and usage information, and entering the virtual memory device into the operation mode (1103, 1105, 1107, 1108).
摘要翻译： 本发明的各种实施例涉及使存储器控制器能够基于动态程序行为为存储器模块的虚拟存储器件选择特定操作模式的方法。 在一个实施例中，一种用于确定存储器模块的每个虚拟存储器设备的操作模式的方法包括：选择度量（1001），其提供在执行一个或多个存储器模块期间优化存储器模块的性能和/或能量效率的标准 多核处理器上的更多应用程序。 对于每个虚拟存储设备（1005），该方法还包括在一段时间内收集与虚拟存储设备相关联的使用信息（1006），基于度量和使用信息确定虚拟存储设备的操作模式（1007） ，并且进入虚拟存储设备进入操作模式（1103,1105,1107,1108）。
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公开(公告)号：US08103675B2
公开(公告)日：2012-01-24
申请号：US12254303
申请日：2008-10-20
IPC分类号： G06F17/16
CPC分类号： G06N5/02
摘要： A method of predicting user-item ratings includes providing a first matrix of hidden variables associated with individual items, a second matrix of hidden variables associated with individual users, a third matrix of predicted user-item ratings derived from an inner product of vectors in the first and second matrices, and a fourth matrix of actual user-item ratings. The first and second matrices are alternately fixed and solved with a weighted-λ regularization of at least one of the first and second matrices by minimizing a sum of squared errors between actual user-item ratings in the fourth matrix and corresponding predicted user-item ratings in the third matrix repeatedly until a stopping criterion is satisfied.
摘要翻译： 预测用户项目评级的方法包括提供与单个项目相关联的隐藏变量的第一矩阵，与个体用户相关联的隐藏变量的第二矩阵，从第三矩阵中的向量的内积导出的预测用户项目等级的第三矩阵 第一和第二矩阵，以及实际用户项目评级的第四矩阵。 第一和第二矩阵通过使第一和第二矩阵中的至少一个矩阵的加权λ正则化被交替固定和求解，通过最小化第四矩阵中的实际用户项目额定值与相应的预测用户项目评级之间的平方误差之和 重复第三矩阵，直到满足停止标准。
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公开(公告)号：US20100100516A1
公开(公告)日：2010-04-22
申请号：US12254303
申请日：2008-10-20
IPC分类号： G06N5/00
CPC分类号： G06N5/02
摘要： A method of predicting user-item ratings includes providing a first matrix of hidden variables associated with individual items, a second matrix of hidden variables associated with individual users, a third matrix of predicted user-item ratings derived from an inner product of vectors in the first and second matrices, and a fourth matrix of actual user-item ratings. The first and second matrices are alternately fixed and solved with a weighted-λ regularization of at least one of the first and second matrices by minimizing a sum of squared errors between actual user-item ratings in the fourth matrix and corresponding predicted user-item ratings in the third matrix repeatedly until a stopping criterion is satisfied.
摘要翻译： 预测用户项目评级的方法包括提供与单个项目相关联的隐藏变量的第一矩阵，与个体用户相关联的隐藏变量的第二矩阵，从第三矩阵中的向量的内积导出的预测用户项目等级的第三矩阵 第一和第二矩阵，以及实际用户项目评级的第四矩阵。 第一和第二矩阵通过使第一和第二矩阵中的至少一个矩阵的加权λ正则化被交替固定和求解，通过最小化第四矩阵中的实际用户项目额定值与相应的预测用户项目评级之间的平方误差之和 重复第三矩阵，直到满足停止标准。
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