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公开(公告)号：US20140059398A1
公开(公告)日：2014-02-27
申请号：US13595282
申请日：2012-08-27
CPC分类号： G06F11/1048 , G11C29/026 , G11C29/028
摘要： Methods and systems are disclosed for adaptive error correction for non-volatile memories that dynamically adjust sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The disclosed methods and systems can also be used with respect to memories that are not non-volatile memories.
摘要翻译： 公开了用于动态调整读出放大器读取检测窗口的非易失性存储器的自适应纠错的方法和系统。 存储器控制电路使用纠错码（ECC）例程来检测使用这些ECC例程不可校正的位错误。 存储器控制电路然后动态地调整读出放大器读取检测窗口以允许确定正确的数据。 校正的数据可以输出到外部电路。 当随后的读取操作尝试访问先前遭受比特故障的地址位置时，也可以存储校正的数据以供稍后访问。 所公开的方法和系统也可以用于不是非易失性存储器的存储器。
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12.发明申请Digital Control For Regulation Of Program Voltages For Non-Volatile Memory (NVM) Systems 有权用于非易失性存储器（NVM）系统的程序电压调节的数字控制公开(公告)号：US20150235704A1
公开(公告)日：2015-08-20
申请号：US14185454
申请日：2014-02-20
摘要： Methods and systems are disclosed for digital control for regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments dynamically adjust program voltages based upon parameters associated with the cells to be programmed in order to account for IR (current-resistance) voltage drops that occur within program voltage distribution lines. Other voltage variations can also be accounted for with these dynamic adjustments, as well. The parameters for cells to be programmed can include, for example, cell address locations for the cells to be programmed, the number of cells to be programmed, and/or other desired parameters associated with the cells to be programmed. The disclosed embodiments use digital control values obtained from lookup tables based upon the cell parameters to adjust output voltages generated by voltage generation circuit blocks used to program the selected cells thereby tuning the program output voltage level to a predetermined desired level.
摘要翻译： 公开了用于数字控制以调节非易失性存储器（NVM）系统的编程电压的方法和系统。 所公开的实施例基于与要编程的单元相关联的参数来动态地调节编程电压，以便考虑在编程电压分配线内发生的IR（电流 - 电阻）电压降。 也可以通过这些动态调整来考虑其他电压变化。 要编程的单元的参数可以包括例如要编程的单元的单元地址位置，要编程的单元的数量，和/或与要编程的单元相关联的其它期望的参数。 所公开的实施例使用基于单元参数从查找表获得的数字控制值来调整由用于编程所选择的单元的电压产生电路块产生的输出电压，从而将程序输出电压电平调谐到预定的期望电平。
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13.发明授权Sector-based regulation of program voltages for non-volatile memory (NVM) systems 有权基于部门的非易失性存储器（NVM）系统的程序电压调节公开(公告)号：US09013927B1
公开(公告)日：2015-04-21
申请号：US14050962
申请日：2013-10-10
CPC分类号： G11C29/021 , G11C5/145 , G11C8/12 , G11C16/08 , G11C16/12 , G11C16/30 , G11C29/028 , G11C2029/1202
摘要： Methods and systems are disclosed for sector-based regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments regulate program voltages for NVM cells based upon feedback signals generated from sector return voltages that are associated with program voltage drivers that are driving program voltages to NVM cells within selected sectors an NVM array. As such, drops in program voltage levels due to IR (current-resistance) voltage losses in program voltage distribution lines are effectively addressed. This sector-based regulation of the program voltage effectively maintains the desired program voltage at the cells being programmed regardless of the sector being accessed for programming and the number of cells being programmed. Sector return voltages can also be used along with local program voltages to provide two-step feedback regulation for the voltage generation circuitry. Test mode configurations can also be provided using test input and/or output pads.
摘要翻译： 公开了用于非易失性存储器（NVM）系统的用于基于扇区的程序电压调节的方法和系统。 所公开的实施例基于从扇区返回电压产生的反馈信号来调节NVM单元的编程电压，所述反馈信号与将编程电压相关联的程序电压驱动到选定扇区内的NVM单元NVM阵列。 因此，编程电压分配线中的IR（电流 - 电阻）电压损失导致的编程电压电平下降被有效地解决。 程序电压的基于扇区的调节在编程的单元有效地保持所需的编程电压，而不管正在被访问的扇区用于编程和正被编程的单元的数量。 扇区返回电压也可以与本地编程电压一起使用，为电压产生电路提供两步反馈调节。 也可以使用测试输入和/或输出焊盘提供测试模式配置。
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14.发明申请SECTOR-BASED REGULATION OF PROGRAM VOLTAGES FOR NON-VOLATILE MEMORY (NVM) SYSTEMS 有权针对非易失性存储器（NVM）系统的程序电压的基于行业的规范公开(公告)号：US20150103602A1
公开(公告)日：2015-04-16
申请号：US14050962
申请日：2013-10-10
IPC分类号： G11C16/10
CPC分类号： G11C29/021 , G11C5/145 , G11C8/12 , G11C16/08 , G11C16/12 , G11C16/30 , G11C29/028 , G11C2029/1202
摘要： Methods and systems are disclosed for sector-based regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments regulate program voltages for NVM cells based upon feedback signals generated from sector return voltages that are associated with program voltage drivers that are driving program voltages to NVM cells within selected sectors an NVM array. As such, drops in program voltage levels due to IR (current-resistance) voltage losses in program voltage distribution lines are effectively addressed. This sector-based regulation of the program voltage effectively maintains the desired program voltage at the cells being programmed regardless of the sector being accessed for programming and the number of cells being programmed. Sector return voltages can also be used along with local program voltages to provide two-step feedback regulation for the voltage generation circuitry. Test mode configurations can also be provided using test input and/or output pads.
摘要翻译： 公开了用于非易失性存储器（NVM）系统的用于基于扇区的程序电压调节的方法和系统。 所公开的实施例基于从扇区返回电压产生的反馈信号来调节NVM单元的编程电压，所述反馈信号与将编程电压相关联的程序电压驱动到选定扇区内的NVM单元NVM阵列。 因此，编程电压分配线中的IR（电流 - 电阻）电压损失导致的编程电压电平下降被有效地解决。 程序电压的基于扇区的调节在编程的单元有效地保持所需的编程电压，而不管正在被访问的扇区用于编程以及正被编程的单元的数量。 扇区返回电压也可以与本地编程电压一起使用，为电压产生电路提供两步反馈调节。 也可以使用测试输入和/或输出焊盘提供测试模式配置。
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公开(公告)号：US20130265828A1
公开(公告)日：2013-10-10
申请号：US13441335
申请日：2012-04-06
IPC分类号： G11C16/10
CPC分类号： G11C16/30 , G11C5/145 , G11C8/08 , G11C16/3454
摘要： A semiconductor memory device includes a non-volatile memory, a memory controller, and a charge pump system. The memory controller establishes first parameters for a first programming cycle of a first plurality of memory cells of the non-volatile memory prior to the first programming cycle being performed. The charge pump system includes a plurality of charge pumps and provides a first programming pulse for use in performing the first program cycle. The first programming pulse is provided by selecting, according to the first parameters, which of the plurality of charge pumps are to be enabled during the first program cycle and which are to be disabled during the first program cycle.
摘要翻译： 半导体存储器件包括非易失性存储器，存储器控制器和电荷泵系统。 存储器控制器在执行第一编程周期之前为非易失性存储器的第一多个存储器单元的第一编程周期建立第一参数。 电荷泵系统包括多个电荷泵并提供用于执行第一程序循环的第一编程脉冲。 第一编程脉冲通过根据第一参数选择在第一编程周期期间启用多个电荷泵中的哪一个并在第一编程周期期间被禁用来提供。
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公开(公告)号：US08704587B2
公开(公告)日：2014-04-22
申请号：US13555848
申请日：2012-07-23
CPC分类号： G11C16/30 , G11C5/145 , H02M3/07 , H02M2001/0022
摘要： A configurable multistage charge pump including multiple pumpcells, at least one bypass switch and control logic. The pumpcells are coupled together in series including a first pumpcell receiving an input voltage and at least one remaining pumpcell including a last pumpcell which generates an output voltage. Each bypass switch is coupled to selectively provide the input voltage to a pumpcell input of a corresponding one of the remaining pumpcells. The control logic is configured to determine one of multiple voltage ranges of the input voltage, to enable each pumpcell for a first voltage range and to disable and bypass at least one pumpcell for at least one other voltage range. A method of operating a multistage charge pump including detecting an input voltage, selecting a voltage range based on an input voltage, and enabling a number of cascaded pumpcells corresponding to the selected voltage range.
摘要翻译： 一个可配置的多级电荷泵，包括多个泵浦单元，至少一个旁路开关和控制逻辑。 泵浦单元串联连接在一起，包括接收输入电压的第一泵浦单元和至少一个包括产生输出电压的最后一个泵浦单元的剩余泵浦单元。 每个旁路开关被耦合以选择性地将输入电压提供给相应的剩余泵浦单元的泵单元输入。 控制逻辑被配置为确定输入电压的多个电压范围中的一个，以使得每个泵浦电池能够达到第一电压范围，并且在至少一个其它电压范围内禁用和旁路至少一个泵浦电池。 一种操作多级电荷泵的方法，包括检测输入电压，基于输入电压选择电压范围，以及使能与选定电压范围对应的多个级联泵浦电池。
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公开(公告)号：US20110050326A1
公开(公告)日：2011-03-03
申请号：US12549499
申请日：2009-08-28
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M2003/077
摘要： A charge pump charges a first capacitor to a predetermined input voltage using a first switch. The first switch is coupled to a first terminal of the first capacitor for coupling the first terminal to an input terminal that receives the predetermined input voltage. A second switch couples a second terminal of the first capacitor to a reference voltage terminal. Charge is sequentially transferred from the first capacitor to an output capacitance by using the first switch. A portion of charge is sequentially removed from the output capacitance to the input terminal using a third switch and a second capacitor. Configuration logic provides control signals to make one or more of a plurality of charge transfer capacitors switch the same as said first capacitor switches.
摘要翻译： 电荷泵使用第一开关将第一电容器充电至预定的输入电压。 第一开关耦合到第一电容器的第一端子，用于将第一端子耦合到接收预定输入电压的输入端子。 第二开关将第一电容器的第二端子耦合到参考电压端子。 通过使用第一开关将充电从第一电容器依次传送到输出电容。 使用第三开关和第二电容器将一部分电荷从输出电容顺序地移除到输入端。 配置逻辑提供控制信号以使得多个电荷转移电容器中的一个或多个与所述第一电容器开关相同。
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18.发明申请Built-In Self-Calibration (BISC) Technique for Regulation Circuits Used in Non-Volatile Memory 有权用于非易失性存储器的调节电路的内置自校准（BISC）技术公开(公告)号：US20090243571A1
公开(公告)日：2009-10-01
申请号：US12055538
申请日：2008-03-26
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： A reference voltage regulation circuit (143) is provided in which one or more input voltage signals (Vref, Vref′) are selectively coupled to a configurable amplifier (114) which is coupled through a sample and hold circuit (120) to a voltage follower circuit (122) which is coupled in feedback to the configurable amplifier (114) for generating an adjusted output voltage at a circuit output (130), where the voltage follow circuit comprises a resistor divider circuit (126) that is controlled by a calibration signal (Cal ) generated by a counter circuit (128) selectively coupled to the output of the configurable amplifier when configured as a comparator for generating the calibration signal in response to a clock signal, where the calibration signal represents a voltage error component (Verror, Voffset) that is removed from the circuit output when the calibration signal is applied to the resistor divider circuit during normal operational.
摘要翻译： 提供了参考电压调节电路（143），其中一个或多个输入电压信号（Vref，Vref'）选择性地耦合到可配置放大器（114），可配置放大器（114）通过采样和保持电路（120）耦合到电压跟随器 电路（122），其反馈耦合到可配置放大器（114），用于在电路输出（130）处产生调整的输出电压，其中电压跟随电路包括由校准信号控制的电阻分压器电路（126） 当被配置为响应于时钟信号产生校准信号的比较器时，选择性地耦合到可配置放大器的输出的计数器电路（128）产生的校准电路（Cal
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公开(公告)号：US20090039942A1
公开(公告)日：2009-02-12
申请号：US11835552
申请日：2007-08-08
IPC分类号： H03L5/00
CPC分类号： H03K3/35613
摘要： A level converter comprises first and second latches, and first through fourth transistors. The first latch has first and second power supply terminals, and first and second nodes. The second latch has third and fourth power supply terminals, and third and fourth nodes. The first transistor has a first current electrode coupled to the first node, a control electrode coupled to receive a first bias voltage, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the third node, and a control electrode coupled to receive a second bias voltage. The third transistor has a first current electrode coupled to the second node, a control electrode coupled to receive the first bias voltage, and a second current electrode. The fourth transistor has a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to receive the second bias voltage, and a second current electrode coupled to the fourth node.
摘要翻译： 电平转换器包括第一和第二锁存器以及第一至第四晶体管。 第一锁存器具有第一和第二电源端子以及第一和第二节点。 第二锁存器具有第三和第四电源端子，以及第三和第四节点。 第一晶体管具有耦合到第一节点的第一电流电极，耦合以接收第一偏置电压的控制电极和第二电流电极。 第二晶体管具有耦合到第一晶体管的第二电流电极的第一电流电极，耦合到第三节点的第二电流电极和耦合以接收第二偏置电压的控制电极。 第三晶体管具有耦合到第二节点的第一电流电极，耦合以接收第一偏置电压的控制电极和第二电流电极。 第四晶体管具有耦合到第三晶体管的第二电流电极的第一电流电极，耦合以接收第二偏置电压的控制电极和耦合到第四节点的第二电流电极。
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公开(公告)号：USD366871S
公开(公告)日：1996-02-06
申请号：US10686
申请日：1993-07-14
申请人： Eric Richardson , Jeffrey B. Postupack , Paul W. Brown , Clifford Sielitsky , Peter Phillips , Steven Maker , Lee A. McDavid , Robert Merrill , J. Alan Witmer , William Leathers , Matt P. Bucy , Jeffrey W. Doyle , Michael Geilich , Eric Gottesman , Gerald F. Halstead , Lannelle Jalowiec , Linda J. Donley , Richard Rosenzweig , Troy D. Andrews , Jeffrey C. Cunningham , Alexander Kish , Timothy Pinkham , David Russell , Lisa J. Thompson , Wu-Cheng Tsai , Robert Bristow-Johnson , Tyler Brown , Milton A. Colvin , Cameron W. Jones , Scott C. Peer , Ivor Taylor , Richard Wear , Dave Oren , Mickey Matsumoto
设计人： Eric Richardson , Jeffrey B. Postupack , Paul W. Brown , Clifford Sielitsky , Peter Phillips , Steven Maker , Lee A. McDavid , Robert Merrill , J. Alan Witmer , William Leathers , Matt P. Bucy , Jeffrey W. Doyle , Michael Geilich , Eric Gottesman , Gerald F. Halstead , Lannelle Jalowiec , Linda J. Donley , Richard Rosenzweig , Troy D. Andrews , Jeffrey C. Cunningham , Alexander Kish , Timothy Pinkham , David Russell , Lisa J. Thompson , Wu-Cheng Tsai , Robert Bristow-Johnson , Tyler Brown , Milton A. Colvin , Cameron W. Jones , Scott C. Peer , Ivor Taylor , Richard Wear , Dave Oren , Mickey Matsumoto
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