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公开(公告)号：US09111629B2
公开(公告)日：2015-08-18
申请号：US13441335
申请日：2012-04-06
CPC分类号： G11C16/30 , G11C5/145 , G11C8/08 , G11C16/3454
摘要： A semiconductor memory device includes a non-volatile memory, a memory controller, and a charge pump system. The memory controller establishes first parameters for a first programming cycle of a first plurality of memory cells of the non-volatile memory prior to the first programming cycle being performed. The charge pump system includes a plurality of charge pumps and provides a first programming pulse for use in performing the first program cycle. The first programming pulse is provided by selecting, according to the first parameters, which of the plurality of charge pumps are to be enabled during the first program cycle and which are to be disabled during the first program cycle.
摘要翻译： 半导体存储器件包括非易失性存储器，存储器控制器和电荷泵系统。 存储器控制器在执行第一编程周期之前为非易失性存储器的第一多个存储器单元的第一编程周期建立第一参数。 电荷泵系统包括多个电荷泵并提供用于执行第一程序循环的第一编程脉冲。 第一编程脉冲通过根据第一参数选择在第一编程周期期间启用多个电荷泵中的哪一个并在第一编程周期期间被禁用来提供。
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公开(公告)号：US08704587B2
公开(公告)日：2014-04-22
申请号：US13555848
申请日：2012-07-23
CPC分类号： G11C16/30 , G11C5/145 , H02M3/07 , H02M2001/0022
摘要： A configurable multistage charge pump including multiple pumpcells, at least one bypass switch and control logic. The pumpcells are coupled together in series including a first pumpcell receiving an input voltage and at least one remaining pumpcell including a last pumpcell which generates an output voltage. Each bypass switch is coupled to selectively provide the input voltage to a pumpcell input of a corresponding one of the remaining pumpcells. The control logic is configured to determine one of multiple voltage ranges of the input voltage, to enable each pumpcell for a first voltage range and to disable and bypass at least one pumpcell for at least one other voltage range. A method of operating a multistage charge pump including detecting an input voltage, selecting a voltage range based on an input voltage, and enabling a number of cascaded pumpcells corresponding to the selected voltage range.
摘要翻译： 一个可配置的多级电荷泵，包括多个泵浦单元，至少一个旁路开关和控制逻辑。 泵浦单元串联连接在一起，包括接收输入电压的第一泵浦单元和至少一个包括产生输出电压的最后一个泵浦单元的剩余泵浦单元。 每个旁路开关被耦合以选择性地将输入电压提供给相应的剩余泵浦单元的泵单元输入。 控制逻辑被配置为确定输入电压的多个电压范围中的一个，以使得每个泵浦电池能够达到第一电压范围，并且在至少一个其它电压范围内禁用和旁路至少一个泵浦电池。 一种操作多级电荷泵的方法，包括检测输入电压，基于输入电压选择电压范围，以及使能与选定电压范围对应的多个级联泵浦电池。
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公开(公告)号：US20140022005A1
公开(公告)日：2014-01-23
申请号：US13555848
申请日：2012-07-23
IPC分类号： G05F1/02
CPC分类号： G11C16/30 , G11C5/145 , H02M3/07 , H02M2001/0022
摘要： A configurable multistage charge pump including multiple pumpcells, at least one bypass switch and control logic. The pumpcells are coupled together in series including a first pumpcell receiving an input voltage and at least one remaining pumpcell including a last pumpcell which generates an output voltage. Each bypass switch is coupled to selectively provide the input voltage to a pumpcell input of a corresponding one of the remaining pumpcells. The control logic is configured to determine one of multiple voltage ranges of the input voltage, to enable each pumpcell for a first voltage range and to disable and bypass at least one pumpcell for at least one other voltage range. A method of operating a multistage charge pump including detecting an input voltage, selecting a voltage range based on an input voltage, and enabling a number of cascaded pumpcells corresponding to the selected voltage range.
摘要翻译： 一个可配置的多级电荷泵，包括多个泵浦单元，至少一个旁路开关和控制逻辑。 泵浦单元串联连接在一起，包括接收输入电压的第一泵浦单元和至少一个包括产生输出电压的最后一个泵浦单元的剩余泵浦单元。 每个旁路开关被耦合以选择性地将输入电压提供给相应的剩余泵浦单元的泵单元输入。 控制逻辑被配置为确定输入电压的多个电压范围中的一个，以使得每个泵浦电池能够达到第一电压范围，并且在至少一个其它电压范围内禁用和旁路至少一个泵浦电池。 一种操作多级电荷泵的方法，包括检测输入电压，基于输入电压选择电压范围，以及使能与选定电压范围对应的多个级联泵浦电池。
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公开(公告)号：US20130265828A1
公开(公告)日：2013-10-10
申请号：US13441335
申请日：2012-04-06
IPC分类号： G11C16/10
CPC分类号： G11C16/30 , G11C5/145 , G11C8/08 , G11C16/3454
摘要： A semiconductor memory device includes a non-volatile memory, a memory controller, and a charge pump system. The memory controller establishes first parameters for a first programming cycle of a first plurality of memory cells of the non-volatile memory prior to the first programming cycle being performed. The charge pump system includes a plurality of charge pumps and provides a first programming pulse for use in performing the first program cycle. The first programming pulse is provided by selecting, according to the first parameters, which of the plurality of charge pumps are to be enabled during the first program cycle and which are to be disabled during the first program cycle.
摘要翻译： 半导体存储器件包括非易失性存储器，存储器控制器和电荷泵系统。 存储器控制器在执行第一编程周期之前为非易失性存储器的第一多个存储器单元的第一编程周期建立第一参数。 电荷泵系统包括多个电荷泵并提供用于执行第一程序循环的第一编程脉冲。 第一编程脉冲通过根据第一参数选择在第一编程周期期间启用多个电荷泵中的哪一个并在第一编程周期期间被禁用来提供。
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公开(公告)号：US08310877B2
公开(公告)日：2012-11-13
申请号：US12985724
申请日：2011-01-06
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/14 , G11C11/5642 , G11C16/10 , G11C16/3418
摘要： A method and memory are provided for determining a read reference level for a plurality of non-volatile memory cells. The method includes: performing a program operation of the plurality of non-volatile memory cells; determining a program level of a least programmed memory cell of the plurality of memory cells; performing an erase operation of the plurality of non-volatile memory cells; determining an erase level of a least erased memory cell of the plurality of memory cells; determining an operating window between the program level and the erase level; and setting the read reference level to be a predetermined offset from the erase level if the operating window is determined to compare favorably to a predetermined value. The memory includes registers for storing the program level and the erase level.
摘要翻译： 提供了一种用于确定多个非易失性存储器单元的读取参考电平的方法和存储器。 该方法包括：执行多个非易失性存储单元的编程操作; 确定所述多个存储器单元中的最小程序存储单元的程序级; 执行所述多个非易失性存储单元的擦除操作; 确定所述多个存储器单元中最少擦除的存储单元的擦除电平; 确定程序级和擦除级之间的操作窗口; 并且如果确定操作窗口与预定值相比较，则将读取参考电平设置为与擦除电平的预定偏移。 存储器包括用于存储程序电平和擦除电平的寄存器。
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公开(公告)号：US20120176844A1
公开(公告)日：2012-07-12
申请号：US12985724
申请日：2011-01-06
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C11/14 , G11C11/5642 , G11C16/10 , G11C16/3418
摘要： A method and memory are provided for determining a read reference level for a plurality of non-volatile memory cells. The method includes: performing a program operation of the plurality of non-volatile memory cells; determining a program level of a least programmed memory cell of the plurality of memory cells; performing an erase operation of the plurality of non-volatile memory cells; determining an erase level of a least erased memory cell of the plurality of memory cells; determining an operating window between the program level and the erase level; and setting the read reference level to be a predetermined offset from the erase level if the operating window is determined to compare favorably to a predetermined value. The memory includes registers for storing the program level and the erase level.
摘要翻译： 提供了一种用于确定多个非易失性存储器单元的读取参考电平的方法和存储器。 该方法包括：执行多个非易失性存储单元的编程操作; 确定所述多个存储器单元中的最小程序存储单元的程序级; 执行所述多个非易失性存储单元的擦除操作; 确定所述多个存储器单元中最少擦除的存储单元的擦除电平; 确定程序级和擦除级之间的操作窗口; 并且如果确定操作窗口与预定值相比较，则将读取参考电平设置为与擦除电平的预定偏移。 存储器包括用于存储程序电平和擦除电平的寄存器。
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7.发明授权Sector-based regulation of program voltages for non-volatile memory (NVM) systems 有权基于部门的非易失性存储器（NVM）系统的程序电压调节公开(公告)号：US09013927B1
公开(公告)日：2015-04-21
申请号：US14050962
申请日：2013-10-10
CPC分类号： G11C29/021 , G11C5/145 , G11C8/12 , G11C16/08 , G11C16/12 , G11C16/30 , G11C29/028 , G11C2029/1202
摘要： Methods and systems are disclosed for sector-based regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments regulate program voltages for NVM cells based upon feedback signals generated from sector return voltages that are associated with program voltage drivers that are driving program voltages to NVM cells within selected sectors an NVM array. As such, drops in program voltage levels due to IR (current-resistance) voltage losses in program voltage distribution lines are effectively addressed. This sector-based regulation of the program voltage effectively maintains the desired program voltage at the cells being programmed regardless of the sector being accessed for programming and the number of cells being programmed. Sector return voltages can also be used along with local program voltages to provide two-step feedback regulation for the voltage generation circuitry. Test mode configurations can also be provided using test input and/or output pads.
摘要翻译： 公开了用于非易失性存储器（NVM）系统的用于基于扇区的程序电压调节的方法和系统。 所公开的实施例基于从扇区返回电压产生的反馈信号来调节NVM单元的编程电压，所述反馈信号与将编程电压相关联的程序电压驱动到选定扇区内的NVM单元NVM阵列。 因此，编程电压分配线中的IR（电流 - 电阻）电压损失导致的编程电压电平下降被有效地解决。 程序电压的基于扇区的调节在编程的单元有效地保持所需的编程电压，而不管正在被访问的扇区用于编程和正被编程的单元的数量。 扇区返回电压也可以与本地编程电压一起使用，为电压产生电路提供两步反馈调节。 也可以使用测试输入和/或输出焊盘提供测试模式配置。
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8.发明申请SECTOR-BASED REGULATION OF PROGRAM VOLTAGES FOR NON-VOLATILE MEMORY (NVM) SYSTEMS 有权针对非易失性存储器（NVM）系统的程序电压的基于行业的规范公开(公告)号：US20150103602A1
公开(公告)日：2015-04-16
申请号：US14050962
申请日：2013-10-10
IPC分类号： G11C16/10
CPC分类号： G11C29/021 , G11C5/145 , G11C8/12 , G11C16/08 , G11C16/12 , G11C16/30 , G11C29/028 , G11C2029/1202
摘要： Methods and systems are disclosed for sector-based regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments regulate program voltages for NVM cells based upon feedback signals generated from sector return voltages that are associated with program voltage drivers that are driving program voltages to NVM cells within selected sectors an NVM array. As such, drops in program voltage levels due to IR (current-resistance) voltage losses in program voltage distribution lines are effectively addressed. This sector-based regulation of the program voltage effectively maintains the desired program voltage at the cells being programmed regardless of the sector being accessed for programming and the number of cells being programmed. Sector return voltages can also be used along with local program voltages to provide two-step feedback regulation for the voltage generation circuitry. Test mode configurations can also be provided using test input and/or output pads.
摘要翻译： 公开了用于非易失性存储器（NVM）系统的用于基于扇区的程序电压调节的方法和系统。 所公开的实施例基于从扇区返回电压产生的反馈信号来调节NVM单元的编程电压，所述反馈信号与将编程电压相关联的程序电压驱动到选定扇区内的NVM单元NVM阵列。 因此，编程电压分配线中的IR（电流 - 电阻）电压损失导致的编程电压电平下降被有效地解决。 程序电压的基于扇区的调节在编程的单元有效地保持所需的编程电压，而不管正在被访问的扇区用于编程以及正被编程的单元的数量。 扇区返回电压也可以与本地编程电压一起使用，为电压产生电路提供两步反馈调节。 也可以使用测试输入和/或输出焊盘提供测试模式配置。
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公开(公告)号：US09685339B2
公开(公告)日：2017-06-20
申请号：US13873917
申请日：2013-04-30
IPC分类号： H01L27/115 , H01L21/28 , H01L29/423 , H01L27/11521
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/42332
摘要： A split gate memory array includes a first row having memory cells; a second row having memory cells, wherein the second row is adjacent to the first row; and a plurality of segments. Each segment includes a first plurality of memory cells of the first row, a second plurality of memory cells of the second row, a first control gate portion which forms a control gate of each memory cell of the first plurality of memory cells, and a second control gate portion which forms a control gate of each memory cell of the second plurality of memory cells. The first control gate portion and the second control gate portion converge to a single control gate portion between neighboring segments of the plurality of segments.
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公开(公告)号：US08971147B2
公开(公告)日：2015-03-03
申请号：US13663636
申请日：2012-10-30
申请人： Gilles Muller , Ronald J. Syzdek
发明人： Gilles Muller , Ronald J. Syzdek
CPC分类号： G11C8/08 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/26 , G11C16/30
摘要： A memory having an array of multi-gate memory cells and a word line driver circuit coupled to a sector of memory cells of the array. In at least one mode of operation, the word line driver circuit is controllable to place an associated control gate word line coupled to the control gate word line driver and coupled to the sector in a floating state during a read operation where the sector is a non selected sector.
摘要翻译： 具有多栅极存储器单元阵列的存储器和耦合到阵列的存储器单元的扇区的字线驱动器电路。 在至少一种操作模式中，字线驱动器电路是可控制的，以将耦合到控制栅极字线驱动器的相关联的控制栅极字线放置在浮动状态下，在读取操作期间扇区是非线性的， 选定部门。
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