MEMORY SYSTEMS HAVING REDUCED MEMORY CHANNEL TRAFFIC AND METHODS FOR OPERATING THE SAME

    公开(公告)号:US20200334105A1

    公开(公告)日:2020-10-22

    申请号:US16385574

    申请日:2019-04-16

    Inventor: AMIT BERMAN

    Abstract: A storage device includes a nonvolatile memory (NVM) device having a plurality of memory blocks and a control circuit configured to perform a read for copy-back operation in response to a receipt of a corresponding command. The control circuit performs the read for copy-back operation by reading page data from a source memory block of the plurality, generating a syndrome from the read page data, outputting the syndrome, receiving error location data in response to outputting the syndrome, correcting the read page data using the received error location data, and writing the corrected read page data to a target memory block among the plurality.

    MEMORY WITH ADAPTIVE SLOW-CELL DATA COMPRESSION

    公开(公告)号:US20210366559A1

    公开(公告)日:2021-11-25

    申请号:US16882031

    申请日:2020-05-22

    Inventor: AMIT BERMAN

    Abstract: An apparatus and method are provided for memory programming, including receiving a first write data unit including a plurality of data bits; programming by at least one pulse the plurality of data bits to the plurality of memory cells; determining if a number of cells successfully programmed by the at least one pulse is less than a threshold; and if the number of cells successfully programmed by the at least one pulse is less than the threshold, compressing a sparse vector of unsuccessfully programmed data bits, receiving another write data unit, concatenating the vector based on the other write data unit, and programming the concatenated vector to another plurality of memory cells.

    DENOISING OF INTRINSIC SNEAK CURRECT BY CELL LOCATION IN PRAM

    公开(公告)号:US20200335160A1

    公开(公告)日:2020-10-22

    申请号:US16386667

    申请日:2019-04-17

    Inventor: AMIT BERMAN

    Abstract: A method of denoising intrinsic sneak currents in a PRAM memory array of M wordlines and N bitlines includes receiving, by the PRAM memory array, an input read address; and selecting from a table of wordline distances from a sense-amplifier versus estimated optimal currents for those wordline distances an estimated optimal reference current for a distance closest to the received input read address. The reference current determines whether a read current is ‘0’ or ‘1’ and minimizes a bit error rate due to effects of sneak paths and parasitic elements that distorts the read current.

    LOW-POWER DATA TRANSFER FROM BUFFER TO FLASH MEMORY

    公开(公告)号:US20190180793A1

    公开(公告)日:2019-06-13

    申请号:US15836067

    申请日:2017-12-08

    Abstract: A solid-state drive (SSD) may include a volatile buffer such as DRAM, a non-volatile memory (NVM) such as NAND Flash connected to the volatile buffer, and a capacitor connected to both, where the capacitor may have an energy capacity insufficient to supply the buffer and NVM using a normal supply voltage in a normal mode, but sufficient to supply the buffer and NVM using at least one reduced supply voltage in a temporary mode; and a related method may include programming data to the NVM by temporarily reducing the supply voltage to the NVM, and writing data to the NVM using the reduced supply voltage.

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