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公开(公告)号：US20220182073A1
公开(公告)日：2022-06-09
申请号：US17478002
申请日：2021-09-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： KANGSEOK LEE , Geunyeong Yu , Heeyoul Kwak , Hongrak Son , Dongmin Shin , Wijik Lee , Bohwan Jun , Youngjun Hwang
Abstract: A method of responding to a read request from a host includes: obtaining read data from a memory device, performing first iteration ECC decoding on the read data to generate a plurality of pieces of decoded data, selecting one of the plurality of pieces of decoded data as intermediate data as intermediate data, generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails, and outputting the intermediate data to the host when the first iteration ECC decoding succeeds.
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公开(公告)号：US20210125048A1
公开(公告)日：2021-04-29
申请号：US16881963
申请日：2020-05-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehun Jang , Hongrak Son , Changkyu Seol , Pilsang Yoon , Junghyun Hong
Abstract: A neuromorphic package device includes a systolic array package and a controller. The systolic array package includes neuromorphic chips arranged in a systolic array along a first direction and a second direction. The controller communicates with a host controls the neuromorphic chips. Each of the neuromorphic chips sequentially transfers weights of a plurality layers of a neural network system in the first direction to store the weights. A first neuromorphic chip performs a calculation based on stored weights therein and an input data received in the second direction, and provides a result of the calculation to at least one of a second neuromorphic chip and a third neuromorphic chip which are adjacent to the first neuromorphic chip. The at least one of the second and third neuromorphic chips performs a calculation based on a provided result of the calculation and stored weights therein.
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公开(公告)号：US20240395352A1
公开(公告)日：2024-11-28
申请号：US18790881
申请日：2024-07-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kangseok Lee , Geunyeong Yu , Seonghyeog Choi , Hongrak Son , Youngjun Hwang
Abstract: In a method of error correction code (ECC) decoding, normal read data are read from a nonvolatile memory device based on normal read voltages, and a first ECC decoding is performed with respect to the normal read data. When the first ECC decoding results in failure, flip read data are read from the nonvolatile memory device based on flip read voltages corresponding to a flip range of a threshold voltage. Corrected read data are generated based on the flip read data by inverting error candidate bits included in the flip range among bits of the normal read data, and a second ECC decoding is performed with respect to the corrected read voltage. Error correction capability may be enhanced by retrying ECC decoding based on the corrected read data when ECC decoding based on the normal read data results in failure.
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14.发明公开公开(公告)号：US20240128985A1
公开(公告)日：2024-04-18
申请号：US18242834
申请日：2023-09-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Bohwan Jun , Daeyeol Yang , Hongrak Son , Geunyeong Yu , Youngjun Hwang
CPC classification number: H03M13/1105 , H03M13/6575
Abstract: A decoding device and a decoding method which relate to: receiving a codeword; estimating a number of errors included in the received codeword; and decoding the codeword based on the estimated number of errors using at least one of a first parity check matrix and a second parity check matrix, wherein the first parity check matrix corresponds to a first low-density parity check (LDPC) code, and the second parity check matrix corresponds to a second LDPC code, and wherein the first parity check matrix is based on a first code type, and the second parity check matrix is based on a second code type different from the first code type.
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公开(公告)号：US11818243B2
公开(公告)日：2023-11-14
申请号：US17343318
申请日：2021-06-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngsik Moon , Wijik Lee , Hongrak Son
CPC classification number: H04L9/008 , G06F21/602 , H04L9/0869
Abstract: An encryption device includes: a parameter generating circuit configured to generate an encryption parameter including a number of initial valid bits based on an operation scenario; an encryption circuit configured to generate a cipher text by encrypting a plain text received from the outside, based on the encryption parameter; an operation circuit configured to generate a final cipher text by performing a plurality of operations on the cipher text according to the operation scenario and tag, to the final cipher text, history information of the operations performed on the final cipher text; and a decryption circuit configured to generate a decrypted plain text by decrypting the final cipher text and output a number of reliable bits of the decrypted plain text based on the history information.
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Patent Agency Ranking
16.发明授权公开(公告)号：US11189358B2
公开(公告)日：2021-11-30
申请号：US16919187
申请日：2020-07-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seonghyeog Choi , Hongrak Son , Taehyun Song , Hyunsang Cho
Abstract: According to a method of controlling an operation of a nonvolatile memory device using machine learning, operating conditions of the nonvolatile memory device are determined by performing an inferring operation using a machine learning model. Training data that are generated based on feature information and error information are collected, where the error information indicate results of error correction code (ECC) decoding of the nonvolatile memory device. The machine learning model is updated by performing a learning operation based on the training data. Optimized operating conditions for individual user environments are provided by collecting training data in the storage system and performing the learning operation and the inferring operation based on the training data.
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17.发明授权公开(公告)号：US11150987B2
公开(公告)日：2021-10-19
申请号：US16891517
申请日：2020-06-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Changkyu Seol , Hyejeong So , Kwanwoo Noh , Hongrak Son , Pilsang Yoon
Abstract: Channel selection information indicate positions of data bits of input data, positions of error correction code (ECC) parity bits for correcting errors in the input data, and positions of state shaping parity bits. The ECC parity bits and the state shaping parity bits are generated to cause a decrease in a quantity of memory cells, of the plurality of memory cells, in which at least one target state among a plurality of states is programmed. An alignment vector is generated based on aligning the data bits of the input data, the ECC parity bits, and the state shaping parity bits, based on the channel selection information. A codeword is generated based on simultaneously performing state shaping and ECC encoding with respect to the alignment vector. Write data are written in the nonvolatile memory device based on the codeword.
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公开(公告)号：US20240184669A1
公开(公告)日：2024-06-06
申请号：US18218294
申请日：2023-07-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehun Jang , Mankeun Seo , Hongrak Son , Bohwan Jun
IPC: G06F11/10
CPC classification number: G06F11/1044 , G06F11/1012
Abstract: An Error correction code (ECC) decoder including an input manager configured to sequentially receive a first read data including a plurality of data units read from a plurality of sectors in a memory cell array of a nonvolatile memory device, by unit of sector, a pre-decoder configured to sequentially receive the first read data and generate a respective syndrome of each of the data units, and a main decoder configured to sequentially perform a first ECC decoding on the first read data based on the respective syndrome. The input manager includes a defective sector buffer to store a data unit having a minimum expected error count from among data units on which a first ECC decoding is failed. The main decoder performs a second ECC decoding on a defective data unit stored in the defective sector buffer and receives a second read data from a selected sector corresponding to the defective data unit.
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公开(公告)号：US11797381B2
公开(公告)日：2023-10-24
申请号：US17816554
申请日：2022-08-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hanbyeul Na , Jaehun Jang , Hongrak Son
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/0772 , G06F11/1044
Abstract: A storage controller includes parallel input channels configured for simultaneously receiving data from substantially redundant memories, an error estimation unit, a decision unit, an error correction unit and a selection unit. The error estimation unit generates error information by estimating an error level of the plurality of data. The decision unit performs a logical operation on the plurality of data to generate operation data. The error correction unit generates error correction data by correcting an error of the operation data. The selection unit selects one of the operation data or the error correction data based on the error information.
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公开(公告)号：US11664826B2
公开(公告)日：2023-05-30
申请号：US17478002
申请日：2021-09-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kangseok Lee , Geunyeong Yu , Heeyoul Kwak , Hongrak Son , Dongmin Shin , Wijik Lee , Bohwan Jun , Youngjun Hwang
CPC classification number: H03M13/2948 , H03M13/096 , H03M13/1108 , H03M13/1575
Abstract: A method of responding to a read request from a host includes: obtaining read data from a memory device, performing first iteration ECC decoding on the read data to generate a plurality of pieces of decoded data, selecting one of the plurality of pieces of decoded data as intermediate data as intermediate data, generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails, and outputting the intermediate data to the host when the first iteration ECC decoding succeeds.
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