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    Homomorphic operation accelerator and homomorphic operation performing device including the same
    12.
    发明授权
    Homomorphic operation accelerator and homomorphic operation performing device including the same 有权

    公开(公告)号：US11539504B2

    公开(公告)日：2022-12-27

    申请号：US17336625

    申请日：2021-06-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hanbyeul Na ,  Sumin Kim ,  Hongrak Son ,  Junho Shin

    IPC: H04L9/00 ,  H04L9/30 ,  H04L9/08 ,  G06F7/46

    Abstract: A homomorphic operation accelerator includes a plurality of circuits and a homomorphic operation managing circuit. The plurality of circuits may perform homomorphic operations. The homomorphic operation managing circuit may receive cipher text data, homomorphic encryption information and homomorphic operation information from an external device. The homomorphic operation managing circuit may activate or deactivate each of a plurality of enable signals applied to the plurality of circuits based on the homomorphic encryption information and the homomorphic operation information. The homomorphic operation managing circuit may activate or deactivate each of the plurality of circuits based on the plurality of enable signals. The homomorphic encryption information may be associated with a homomorphic encryption algorithm used to generate the cipher text data. The homomorphic operation information may be associated with the homomorphic operations to be performed on the cipher text data.

    Display screen or portion thereof with transitional graphical user interface
    14.
    外观设计
    Display screen or portion thereof with transitional graphical user interface 有权

    公开(公告)号：USD1009062S1

    公开(公告)日：2023-12-26

    申请号：US29829401

    申请日：2022-03-04

    Applicant: Samsung Electronics Co., Ltd.

    Designer： Sumin Kim ,  Jangwon Seo ,  Younga Kim ,  Eunnim Cho ,  Heuijin Kwon

    Abstract: FIG. 1 is a front view of the first image in a sequence for a display screen or portion thereof with transitional graphical user interface showing our new design;
    FIG. 2 is the second image thereof;
    FIG. 3 is the third image thereof;
    FIG. 4 is the fourth image thereof;
    FIG. 5 is the fifth image thereof;
    FIG. 6 is the sixth image thereof;
    FIG. 7 is the seventh image thereof;
    FIG. 8 is the eighth image thereof;
    FIG. 9 is the ninth image thereof;
    FIG. 10 is the tenth image thereof;
    FIG. 11 is the eleventh image thereof;
    FIG. 12 is the twelfth image thereof; and,
    FIG. 13 is the thirteenth image thereof.
    The outer perimeter shown in broken lines illustrates a display screen or portion thereof and forms no part of the design; the remaining broken lines illustrate portions of the transitional graphical user interface that form no part of the design.
    The appearance of the transitional image sequentially transitions between the images shown in FIGS. 1-13. The process or period in which one image transitions to another image forms no part of the claimed design.

    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF CHANNEL PATTERNS
    17.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF CHANNEL PATTERNS 有权

    公开(公告)号：US20210013110A1

    公开(公告)日：2021-01-14

    申请号：US16793097

    申请日：2020-02-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jeongho MUN ,  Naery Yu ,  Sumin Kim ,  Songse Yi

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3213

    Abstract: A semiconductor device manufacturing method includes forming a gate dielectric layer surrounding first semiconductor patterns and second semiconductor patterns; forming a first organic pattern covering the second semiconductor patterns; forming a sacrificial pattern interposed between the first semiconductor patterns and exposing both side surfaces of the first semiconductor patterns, and a conductive pattern surrounding the second semiconductor patterns and disposed between the first organic pattern and the second semiconductor patterns; forming a second organic pattern covering the first semiconductor patterns, the gate dielectric layer, the sacrificial pattern, and the first organic pattern; and forming a cross-linking layer interposed between the first organic material pattern and the second organic material pattern.

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