公开(公告)号：US20250113482A1

公开(公告)日：2025-04-03

申请号：US18980204

申请日：2024-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Taehoon Kim ,  Kyujin Kim ,  Chulkwon Park ,  Sunghee Han ,  Yoosang Hwang

IPC: H10B12/00

Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer.

公开(公告)号：US11889682B2

公开(公告)日：2024-01-30

申请号：US17373539

申请日：2021-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Kyujin Kim ,  Chulkwon Park ,  Sunghee Han

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor memory device includes a substrate comprising a memory cell region and a dummy cell region surrounding the memory cell region, the memory cell region including a plurality of memory cells, a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width in a short axis direction orthogonal to the long axis direction, and a plurality of dummy active regions in the dummy cell region, each extending in the long axis direction, each of the plurality of dummy active regions having a second width greater than the first width in the short axis direction.

公开(公告)号：US11658117B2

公开(公告)日：2023-05-23

申请号：US17667866

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L29/06 ,  G11C5/10 ,  H01L29/423 ,  H01L27/108 ,  H01L21/768

CPC classification number: H01L23/528 ,  G11C5/10 ,  H01L21/76831 ,  H01L27/10888 ,  H01L29/0649 ,  H01L29/4236

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US20220165657A1

公开(公告)日：2022-05-26

申请号：US17667866

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEJIN PARK ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/528 ,  H01L29/06 ,  G11C5/10 ,  H01L29/423 ,  H01L27/108 ,  H01L21/768

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US20220139921A1

公开(公告)日：2022-05-05

申请号：US17372634

申请日：2021-07-12

Applicant: Samsung Electronics Co., Ltd

Inventor： EUNA KIM ,  Keunnam Kim ,  Kiseok Lee ,  Wooyoung Choi ,  Sunghee Han

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes a substrate including an active region, a first bitline structure and a second bitline structure that extend side by side on the substrate, a storage node contact electrically connected to the active region between the first and second bitline structures, a lower landing pad between the first and second bitline structures and on the storage node contact, an upper landing pad in contact with the first bitline structure and electrically connected to the lower landing pad, and a capping insulating layer. A lower surface of the upper landing pad in contact with the first bitline structure and a lower surface of the capping insulating layer in contact with the lower landing pad each include a portion in which a horizontal separation distance is increased from the adjacent upper landing pad in a direction toward the substrate.

公开(公告)号：US11270933B2

公开(公告)日：2022-03-08

申请号：US17038085

申请日：2020-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Il Han ,  Sunghee Han

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: A semiconductor device comprises a substrate including a cell array region and a peripheral circuit region that surrounds the cell array region. The cell array region includes landing pads disposed on the substrate and first bottom electrodes disposed on and connected to corresponding landing pads. The peripheral circuit region includes conductive lines disposed on the substrate, a first conductive pad disposed on and spaced apart from the conductive lines, a dielectric pattern disposed between the conductive lines and the first conductive pad, and a plurality of second bottom electrodes disposed on and connected in common to the first conductive pad. A height of each of the first bottom electrodes is greater than a height of each of the second bottom electrodes. Top surfaces of the first bottom electrodes are located at a same level as a level of top surfaces of the second bottom electrodes.

公开(公告)号：US11043498B1

公开(公告)日：2021-06-22

申请号：US16806667

申请日：2020-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Il Han ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108

Abstract: A semiconductor memory device is provided. The device includes a substrate including a cell region and a peripheral region; a plurality of lower electrodes disposed on the substrate in the cell region; a dielectric layer disposed on the plurality of lower electrodes; a metal containing layer disposed on the dielectric layer; a silicon germanium layer disposed on and electrically connected to the metal containing layer; a conductive pad disposed on and electrically connected to the silicon germanium layer; and an upper electrode contact plug disposed on and electrically connected to the conductive pad; The conductive pad extends from the upper electrode contact plug towards the peripheral region in a first direction, and the silicon germanium layer includes an edge portion that extends past the conductive pad in the first direction.

公开(公告)号：US20210082799A1

公开(公告)日：2021-03-18

申请号：US16879009

申请日：2020-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/528 ,  H01L29/06 ,  H01L21/768 ,  H01L29/423 ,  H01L27/108 ,  G11C5/10

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US10103030B2

公开(公告)日：2018-10-16

申请号：US15377113

申请日：2016-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-sun Min ,  Yoonjae Kim ,  Sooho Shin ,  Sunghee Han

IPC: H01L21/3205 ,  H01L21/306 ,  H01L21/265 ,  H01L21/283 ,  H01L21/308 ,  H01L21/768 ,  H01L21/822 ,  H01L21/033 ,  H01L21/3213 ,  H01L27/108

Abstract: A method of fabricating a semiconductor device includes sequentially forming a first insulation pattern and an etch stop pattern on a peripheral circuit area of a substrate, forming a first mask pattern on a cell array area of the substrate, the first mask pattern including a pair of first portions extending in parallel and a second portion covering a portion of a sidewall of the etch stop pattern and a portion of a sidewall of the first insulation pattern, forming a second insulation layer covering the etch stop pattern and the first mask pattern, partially etching the etch stop pattern and the second insulation layer to expose the second portion of the first mask pattern, and removing the second portion of the first mask pattern to divide the pair of first portions of the first mask pattern.

公开(公告)号：US20160181198A1

公开(公告)日：2016-06-23

申请号：US14971402

申请日：2015-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： DAEIK KIM ,  Jemin Park ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L23/522 ,  H01L29/06 ,  H01L27/108

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855 ,  H01L27/10897 ,  H01L29/4236 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first device isolation region and a second device isolation region defining a first active region, a second active region, and a third active region in a substrate, a recess region exposing an upper surface of the first active region and upper surfaces of the first and second device isolation regions, and active buffer patterns on the second and third active regions. The first active region is located between the second and third active regions, the first device isolation region is located between the first and second active regions, the second device isolation region is located between the first and third active regions. Upper sidewalls of the second and third active regions are exposed in the recess region.

Abstract translation: 半导体器件包括第一器件隔离区和限定衬底中的第一有源区，第二有源区和第三有源区的第二器件隔离区，暴露第一有源区的上表面的凹陷区和上表面 的第一和第二器件隔离区域以及第二和第三有效区域上的主动缓冲器图案。 第一有源区位于第二和第三有源区之间，第一器件隔离区位于第一和第二有源区之间，第二器件隔离区位于第一和第三有源区之间。 第二和第三有源区域的上侧壁在凹陷区域中露出。