公开(公告)号：US11514973B2

公开(公告)日：2022-11-29

申请号：US17003038

申请日：2020-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin Rim ,  Yongho Kim ,  Hoonki Kim

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4097 ,  G11C11/4094 ,  G11C5/14 ,  G11C11/419 ,  G11C11/418 ,  G11C11/413 ,  G11C7/12 ,  G11C11/417 ,  G11C11/416

Abstract: A memory device is provided. The memory device includes a cell array having memory cells; n word lines sequentially arranged and including a first word line, an n-th word line, and word lines interposed between the first word line and the n-th word line; bit lines; a first power node located adjacent to the first word line; a second power node located adjacent to the n-th word line; a first switch connected between the first power node and the cell array; a write driver located adjacent to the n-th word line and connected to the bit lines; and a switch controller configured to control the first switch to isolate the first power node from the memory cells during a write operation on memory cells connected to the first word line.

公开(公告)号：US20190267366A1

公开(公告)日：2019-08-29

申请号：US16407919

申请日：2019-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO DO ,  Woojin Rim ,  Jisu Yu ,  Jonghoon Jung

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  G03F1/36 ,  H01L23/522 ,  G06F17/50 ,  H01L27/118 ,  H01L21/8238 ,  H01L23/485

Abstract: A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

公开(公告)号：US09496027B2

公开(公告)日：2016-11-15

申请号：US14793044

申请日：2015-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woojin Rim ,  Taejoong Song ,  Gyuhong Kim ,  Seong Ook Jung ,  Hanwool Jeong

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/419

Abstract: A static random access memory device may include a write driver configured to float one of a first bitline and a second bitline connected to a memory cell and apply a write voltage to the other bitline in response to a logic state of a data signal; a write failure detector configured to receive a voltage of the floated bitline and output a write failure signal; and an assist voltage generator configured to generate a write assist voltage in response to the write failure signal. The write driver may additionally provide the write assist voltage to a bitline to which the write voltage is applied.

Abstract translation: 静态随机存取存储器装置可以包括写入驱动器，其被配置为浮置连接到存储器单元的第一位线和第二位线之一，并响应于数据信号的逻辑状态向另一个位线施加写入电压; 写入故障检测器，被配置为接收浮动位线的电压并输出写入失败信号; 以及辅助电压发生器，被配置为响应于写入失败信号产生写入辅助电压。 写入驱动器可以另外向写入电压施加到的位线提供写入辅助电压。

公开(公告)号：US20160042784A1

公开(公告)日：2016-02-11

申请号：US14793044

申请日：2015-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woojin Rim ,  Taejoong Song ,  Gyuhong Kim ,  Seong Ook Jung ,  Hanwool Jeong

IPC: G11C11/419 ,  G11C29/02

CPC classification number: G11C11/419

Abstract: A static random access memory device may include a write driver configured to float one of a first bitline and a second bitline connected to a memory cell and apply a write voltage to the other bitline in response to a logic state of a data signal; a write failure detector configured to receive a voltage of the floated bitline and output a write failure signal; and an assist voltage generator configured to generate a write assist voltage in response to the write failure signal. The write driver may additionally provide the write assist voltage to a bitline to which the write voltage is applied.

Abstract translation: 静态随机存取存储器装置可以包括写入驱动器，其被配置为浮置连接到存储器单元的第一位线和第二位线之一，并响应于数据信号的逻辑状态向另一个位线施加写入电压; 写入故障检测器，被配置为接收浮动位线的电压并输出写入失败信号; 以及辅助电压发生器，被配置为响应于写入失败信号产生写入辅助电压。 写入驱动器可以另外向写入电压施加到的位线提供写入辅助电压。