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    CAMERA BRACKET INCLUDING AUDIO SIGNAL PATH AND ELECTRONIC DEVICE INCLUDING THE CAMERA BRACKET
    11.
    发明申请
    CAMERA BRACKET INCLUDING AUDIO SIGNAL PATH AND ELECTRONIC DEVICE INCLUDING THE CAMERA BRACKET 有权

    公开(公告)号：US20220360655A1

    公开(公告)日：2022-11-10

    申请号：US17872101

    申请日：2022-07-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehong JUNG ,  Gyeongtae KIM ,  Yongseok LEE ,  Jinman KIM ,  Souksu JANG ,  Hyeyeong CHOI ,  Jiwoo LEE

    IPC: H04M1/02 ,  G03B17/56 ,  H04N5/225

    Abstract: An electronic device is disclosed herein. The device includes a housing including a first opening formed in a surface thereof, a camera at least partially disposed in the housing, such that a lens of the camera is aligned with the first opening, a camera bracket including a flange structure disposed in the housing and spaced apart from the surface of the housing at a predetermined interval, a protruding structure extending from the flange structure into a space defined between the camera and an inner wall of the first opening to surround at least part of the camera, wherein the flange structure includes a first through-hole, and the protruding structure includes a recess, and wherein the protruding structure and the inner wall of the first opening form a microphone hole in communication with the recess and part of the first opening, an adhesive member disposed between the flange structure and an inner surface of the housing, the adhesive member including a passage, wherein one side of the passage is connected to the recess, and an opposite side of the passage is connected to the first through-hole, and a microphone element disposed in the housing and aligned with the first through-hole.

    CRYSTAL OSCILLATOR REDUCING PHASE NOISE AND SEMICONDUCTOR CHIP INCLUDING THE SAME
    12.
    发明申请
    CRYSTAL OSCILLATOR REDUCING PHASE NOISE AND SEMICONDUCTOR CHIP INCLUDING THE SAME 有权

    公开(公告)号：US20220094302A1

    公开(公告)日：2022-03-24

    申请号：US17340593

    申请日：2021-06-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehong JUNG ,  Wonkang KIM ,  Seungjin KIM ,  Seunghyun OH

    IPC: H03B5/36 ,  H03K5/159 ,  G06F1/10

    Abstract: A crystal oscillator reducing phase noise and a semiconductor chip including the same are provided. The crystal oscillator includes a transconductance circuit electrically connected to a crystal, a load capacitor connected to the transconductance circuit, a feedback resistance circuit connected between an input terminal of the transconductance circuit and an output terminal of the transconductance circuit, the feedback resistance circuit configured to provide a feedback resistance, and a variable resistance controller configured to generate a resistance control signal for controlling the feedback resistance, the resistance control signal causing the feedback resistance to have a first value in a first period and a second value in a second period, the first value being less than the second value, the first period corresponding to a first portion of a cycle of the clock signal, and the second period corresponding to a second portion of the cycle different from the first portion.

    FOLDABLE ELECTRONIC APPARATUS INCLUDING PLURALITY OF AUDIO INPUT DEVICES
    13.
    发明申请
    FOLDABLE ELECTRONIC APPARATUS INCLUDING PLURALITY OF AUDIO INPUT DEVICES 有权

    公开(公告)号：US20220086565A1

    公开(公告)日：2022-03-17

    申请号：US17533651

    申请日：2021-11-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaehong JUNG ,  Minsoo KIM ,  Sangmin LEE ,  Jiwoo LEE

    IPC: H04R1/40 ,  H04R1/02 ,  H04M1/02

    Abstract: An electronic apparatus may include: a foldable housing which includes a hinge structure that can switch the foldable housing between a folding state or an unfolding state, a first housing structure that is connected to the hinge structure and includes a first face oriented in a first direction and a second face oriented in a second direction opposite to the first direction, and a second housing structure that is connected to the hinge structure, includes a third face oriented in a third direction and a fourth face oriented in a fourth direction opposite to the third direction, and comes into contact with the first housing structure by pivoting about the hinge structure; a first display which extends from the first face to the third face and forms the first face and the third face; a second display which forms at least a portion of the fourth face; and at least one audio input device which is disposed on at least one of the second face or the fourth face.

    PHASE-LOCKED LOOP CIRCUIT AND CLOCK GENERATOR INCLUDING THE SAME
    14.
    发明申请
    PHASE-LOCKED LOOP CIRCUIT AND CLOCK GENERATOR INCLUDING THE SAME 有权

    公开(公告)号：US20210111724A1

    公开(公告)日：2021-04-15

    申请号：US17006152

    申请日：2020-08-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehong JUNG ,  Sangdon JUNG ,  Kyungmin LEE ,  Byungki HAN

    IPC: H03L7/081 ,  H03L7/099 ,  H03L7/197 ,  H03L7/091

    Abstract: A phase-locked loop (PLL) circuit may include a voltage-controlled oscillator, a sub-sampling PLL circuit, and a fractional frequency division control circuit. The fractional frequency division control circuit may include a voltage-controlled delay line that routes a feedback signal to generate delay information, a replica voltage-controlled delay line to which the delay information is applied and configured to route a reference clock signal to generate a plurality of delay reference clock signals each delayed by up to a different respective delay time, and a digital-to-time converter (DTC) configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.

    CAMERA BRACKET INCLUDING AUDIO SIGNAL PATH AND ELECTRONIC DEVICE INCLUDING THE CAMERA BRACKET
    15.
    发明申请
    CAMERA BRACKET INCLUDING AUDIO SIGNAL PATH AND ELECTRONIC DEVICE INCLUDING THE CAMERA BRACKET 有权

    公开(公告)号：US20210037125A1

    公开(公告)日：2021-02-04

    申请号：US16944557

    申请日：2020-07-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehong JUNG ,  Gyeongtae KIM ,  Yongseok LEE ,  Jinman KIM ,  Souksu JANG ,  Hyeyeong CHOI ,  Jiwoo LEE

    IPC: H04M1/02 ,  H04N5/225 ,  G03B17/56

    Abstract: An electronic device is disclosed herein. The device includes a housing including a first opening formed in a surface thereof, a camera at least partially disposed in the housing, such that a lens of the camera is aligned with the first opening, a camera bracket including a flange structure disposed in the housing and spaced apart from the surface of the housing at a predetermined interval, a protruding structure extending from the flange structure into a space defined between the camera and an inner wall of the first opening to surround at least part of the camera, wherein the flange structure includes a first through-hole, and the protruding structure includes a recess, and wherein the protruding structure and the inner wall of the first opening form a microphone hole in communication with the recess and part of the first opening, an adhesive member disposed between the flange structure and an inner surface of the housing, the adhesive member including a passage, wherein one side of the passage is connected to the recess, and an opposite side of the passage is connected to the first through-hole, and a microphone element disposed in the housing and aligned with the first through-hole.

    PHASE-LOCKED LOOP (PLL) CIRCUIT AND CLOCK GENERATOR INCLUDING SUB-SAMPLING CIRCUIT
    16.
    发明申请
    PHASE-LOCKED LOOP (PLL) CIRCUIT AND CLOCK GENERATOR INCLUDING SUB-SAMPLING CIRCUIT 有权

    公开(公告)号：US20210021273A1

    公开(公告)日：2021-01-21

    申请号：US16842281

    申请日：2020-04-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaehong JUNG ,  Sangdon JUNG ,  Seunghyun OH ,  Kyungmin LEE

    IPC: H03L7/107 ,  H03L7/089 ,  H03L7/099

    Abstract: A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator configured to generate an output clock, and a sub-sampling PLL circuit configured to receive, from the voltage-controlled oscillator, the generated output clock as feedback, and perform a phase-locking operation on the received output clock. The sub-sampling PLL circuit includes a buffer configured to buffer the received output clock, and the sub-sampling PLL circuit is further configured to adaptively adjust an internal signal to maintain a loop bandwidth of the sub-sampling PLL circuit, based on a change of a characteristic of the buffer according to at least one of process, voltage, and temperature (PVT) change.

    VIDEO SIGNAL PROCESSING METHOD AND APPARATUS USING MULTIPLE TRANSFORM KERNELS
    19.
    发明公开
    VIDEO SIGNAL PROCESSING METHOD AND APPARATUS USING MULTIPLE TRANSFORM KERNELS 审中-公开

    公开(公告)号：US20230362411A1

    公开(公告)日：2023-11-09

    申请号：US18352796

    申请日：2023-07-14

    Applicant: SAMSUNG ELECTRONICS CO, LTD.

    Inventor： Jaehong JUNG ,  Juhyung SON ,  Dongcheol KIM ,  Geonjung KO ,  Jinsam KWAK

    IPC: H04N19/625 ,  H04N19/12 ,  H04N19/176 ,  H04N19/61

    CPC classification number: H04N19/625 ,  H04N19/12 ,  H04N19/176 ,  H04N19/61

    Abstract: A video signal processor is configured to: obtain at least one transform block for a residual signal of a current block from a video signal bitstream, wherein the transform block comprises a plurality of transform coefficients two-dimensionally arranged, determine, on the basis of length information of a first side of the transform block, a horizontal transform kernel for horizontal transformation of the transform block, regardless of a length of a second side of the transform block, which is orthogonal to the first side, determine, on the basis of length information of the second side, a vertical transform kernel for vertical transformation of the transform block, regardless of a length of the first side, obtain the residual signal of the current block by performing, on the transform block, inverse transformation using the horizontal transform kernel and the vertical transform kernel, and reconstruct the current block based on the residual signal.

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