公开(公告)号：US20210111724A1

公开(公告)日：2021-04-15

申请号：US17006152

申请日：2020-08-28

申请人： Samsung Electronics Co., Ltd.

发明人： Jaehong JUNG ,  Sangdon JUNG ,  Kyungmin LEE ,  Byungki HAN

IPC分类号： H03L7/081 ,  H03L7/099 ,  H03L7/197 ,  H03L7/091

摘要： A phase-locked loop (PLL) circuit may include a voltage-controlled oscillator, a sub-sampling PLL circuit, and a fractional frequency division control circuit. The fractional frequency division control circuit may include a voltage-controlled delay line that routes a feedback signal to generate delay information, a replica voltage-controlled delay line to which the delay information is applied and configured to route a reference clock signal to generate a plurality of delay reference clock signals each delayed by up to a different respective delay time, and a digital-to-time converter (DTC) configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.

公开(公告)号：US20210021273A1

公开(公告)日：2021-01-21

申请号：US16842281

申请日：2020-04-07

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jaehong JUNG ,  Sangdon JUNG ,  Seunghyun OH ,  Kyungmin LEE

IPC分类号： H03L7/107 ,  H03L7/089 ,  H03L7/099

摘要： A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator configured to generate an output clock, and a sub-sampling PLL circuit configured to receive, from the voltage-controlled oscillator, the generated output clock as feedback, and perform a phase-locking operation on the received output clock. The sub-sampling PLL circuit includes a buffer configured to buffer the received output clock, and the sub-sampling PLL circuit is further configured to adaptively adjust an internal signal to maintain a loop bandwidth of the sub-sampling PLL circuit, based on a change of a characteristic of the buffer according to at least one of process, voltage, and temperature (PVT) change.