公开(公告)号：US20210111724A1

公开(公告)日：2021-04-15

申请号：US17006152

申请日：2020-08-28

申请人： Samsung Electronics Co., Ltd.

发明人： Jaehong JUNG ,  Sangdon JUNG ,  Kyungmin LEE ,  Byungki HAN

IPC分类号： H03L7/081 ,  H03L7/099 ,  H03L7/197 ,  H03L7/091

摘要： A phase-locked loop (PLL) circuit may include a voltage-controlled oscillator, a sub-sampling PLL circuit, and a fractional frequency division control circuit. The fractional frequency division control circuit may include a voltage-controlled delay line that routes a feedback signal to generate delay information, a replica voltage-controlled delay line to which the delay information is applied and configured to route a reference clock signal to generate a plurality of delay reference clock signals each delayed by up to a different respective delay time, and a digital-to-time converter (DTC) configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.

公开(公告)号：US20210099164A1

公开(公告)日：2021-04-01

申请号：US16866871

申请日：2020-05-05

申请人： Samsung Electronics Co., Ltd.

发明人： Hyungi SEOK ,  Seungjin KIM ,  Byungki HAN ,  Jaehoon LEE

IPC分类号： H03K5/1534 ,  H03K5/24 ,  H03K5/151 ,  H03K3/017

摘要： An electronic device includes: a first equalizing circuit configured to receive a data signal and output a first equalizing signal based on the data signal; a pulse generator configured to generate a first pulse signal and a second pulse signal in response to a rising edge and a falling edge of the data signal, respectively; a second equalizing circuit configured to output a second equalizing signal based on the first pulse signal and the second pulse signal that have been inverted; and an output terminal configured to output an output signal in which the first equalizing signal and the second equalizing signal have been summed.

公开(公告)号：US20160173063A1

公开(公告)日：2016-06-16

申请号：US14908067

申请日：2014-07-24

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Byungki HAN ,  Suseob AHN ,  Jongwoo LEE

IPC分类号： H03H11/12 ,  H03H11/04

CPC分类号： H03H11/12 ,  H03H7/24 ,  H03H11/0405 ,  H03H11/0455 ,  H03H11/1252 ,  H03H11/1291 ,  H03H2011/0494 ,  H03H2250/00 ,  H04L25/03

摘要： A filtering apparatus and method of a multimode multiband transceiver is provided for filtering a signal carrying an analog baseband signal. A filtering apparatus of a multimode multiband radio transceiver of the present invention includes a filtering unit which filters Radio Frequency (RF) signals on one of at least one frequency bands, a switching unit which switches the signals among at least one filter block included in the filtering unit according to a selected communication mode, and a controller which selects the communication mode and controls the switching unit. The analog signal filtering apparatus and method of the present invention is advantageous in terms of providing a variable gain amplifier, filter circuit, and algorithm capable of fulfilling the gains and bandwidths required by the baseband receiver for all mobile communication standards complied by 2G, 3G, and 4G systems.

摘要翻译： 提供了一种多模多频收发器的滤波装置和方法，用于对携带模拟基带信号的信号进行滤波。 本发明的多模多频带无线电收发器的滤波装置包括：滤波单元，其对至少一个频带中的一个频带上的射频（RF）信号进行滤波;切换单元，其在包括在所述至少一个频带中的至少一个滤波器块 过滤单元，以及选择通信模式并控制切换单元的控制器。 本发明的模拟信号滤波装置和方法在提供一种可变增益放大器，滤波器电路和算法方面是有利的，该可变增益放大器，滤波器电路和算法能够满足基带接收机对2G，3G所遵循的所有移动通信标准所需的增益和带宽， 和4G系统。