公开(公告)号：US10978145B2

公开(公告)日：2021-04-13

申请号：US16540862

申请日：2019-08-14

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Peter Rabkin ,  Mohan Dunga ,  Gerrit Jan Hemink ,  Changyuan Chen

IPC: G11C11/56 ,  G11C11/408 ,  G11C11/407 ,  G11C11/406 ,  G11C11/4074

Abstract: Apparatuses and techniques are provided for programming memory cells while reducing widening of a threshold voltage distribution due to changes in the temperature between the time of programming and the time of a subsequent read operation. One technique is based on a correlation between program speed and temperature coefficient (Tco). A different verify test is used for different memory cells which have a common assigned data state according to the program loop number and the temperature. Another technique is based on sensing the memory cells to measure their subthreshold slope and classifying the memory cells into groups. The sensing can occur as a separate operation before programming or as part of the programming of user data. The subsequent programming of the memory cells involves adjusting the verify test of each memory cell based on its group and the temperature.

公开(公告)号：US10566059B2

公开(公告)日：2020-02-18

申请号：US16014028

申请日：2018-06-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Vinh Diep ,  Ching Huang Lu ,  Henry Chin ,  Changyuan Chen

IPC: G11C11/34 ,  G11C16/04 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/11573 ,  H01L29/792 ,  H01L27/11582

Abstract: Systems, methods, and devices of the various embodiments provide both “string-sharing” drain select gate electrodes and “string-selective” drain select gate electrodes in vertical NAND strings. Various embodiments may provide two or more vertical NAND strings sharing a common drain select gate electrode while also having separate additional drain select gate electrodes not electrically connected across the two or more vertical NAND strings.

公开(公告)号：US10204689B1

公开(公告)日：2019-02-12

申请号：US15699513

申请日：2017-09-08

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Anubhav Khandelwal ,  Changyuan Chen ,  Cynthia Hsu ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C11/56

Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

公开(公告)号：US20170358365A1

公开(公告)日：2017-12-14

申请号：US15181346

申请日：2016-06-13

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Gerrit Jan Hemink ,  Mohan Dunga ,  Bijesh Rajamohanan ,  Changyuan Chen

IPC: G11C16/28 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C16/28 ,  G06F11/1068 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/1204

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.