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公开(公告)号：US20210050054A1
公开(公告)日：2021-02-18
申请号：US16540862
申请日：2019-08-14
发明人： Biswajit Ray , Peter Rabkin , Mohan Dunga , Gerrit Jan Hemink , Changyuan Chen
IPC分类号： G11C11/56 , G11C11/406 , G11C11/4074 , G11C11/408
摘要： Apparatuses and techniques are provided for programming memory cells while reducing widening of a threshold voltage distribution due to changes in the temperature between the time of programming and the time of a subsequent read operation. One technique is based on a correlation between program speed and temperature coefficient (Tco). A different verify test is used for different memory cells which have a common assigned data state according to the program loop number and the temperature. Another technique is based on sensing the memory cells to measure their subthreshold slope and classifying the memory cells into groups. The sensing can occur as a separate operation before programming or as part of the programming of user data. The subsequent programming of the memory cells involves adjusting the verify test of each memory cell based on its group and the temperature.
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公开(公告)号：US20170372789A1
公开(公告)日：2017-12-28
申请号：US15194295
申请日：2016-06-27
发明人： Biswajit Ray , Mohan Dunga , Gerrit Jan Hemink , Changyuan Chen
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/08 , G11C16/16
摘要： Apparatuses, systems, methods, and computer program products are disclosed for erase depth control. One apparatus includes a block of non-volatile storage cells. A controller is configured to perform a first erase operation on a block of non-volatile storage cells. A controller for a block is configured to determine a first set of storage cells of the block having a faster erase speed than a second set of storage cells of the block based on a verify voltage threshold. A controller for a block is configured to perform a second erase operation on the block using different voltages for a first set of storage cells and a second set of storage cells of the block.
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公开(公告)号：US20210104280A1
公开(公告)日：2021-04-08
申请号：US16593393
申请日：2019-10-04
发明人： Sung-Chul Lee , Ching-Huang Lu , Henry Chin , Changyuan Chen
摘要： Method for performing an erase program operation. Various methods include: erasing a block of cells by: applying a program pulse to a block of memory elements in the three-dimensional memory that programs the block of memory elements to a level below an erase verify level, where the three-dimensional memory comprises memory elements stacked vertically; performing a verify step to verify voltage levels of a group of memory elements; determining that a memory element of the group is outside of a threshold window defined between the erase verify level and a compact erase threshold amount; and applying a second program pulse to the memory element. Where erasing the block of memory elements creates an erased block, where a width of the voltage distribution of the erased memory elements in the erased block is the same as or below a width of a voltage distribution associated with programmed memory elements.
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公开(公告)号：US10074440B2
公开(公告)日：2018-09-11
申请号：US15337522
申请日：2016-10-28
发明人： Biswajit Ray , Mohan Dunga , Changyuan Chen
CPC分类号： G11C16/3431 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/28 , G11C16/3418 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C16/3495
摘要： An erase operation includes one or more erase depth checks to detect the occurrence of shallow erased memory cells at the end of an erase process. Memory cells are subjected to erase and erase verification until erase verification success is achieved. At the end of successful erase verification, a subset of memory cells is read to detect an erase depth or level of the memory cells. If the erase depth check indicates that the subset memory cells are in a shallow erased condition, additional erasing and verification is performed.
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公开(公告)号：US20180122489A1
公开(公告)日：2018-05-03
申请号：US15337522
申请日：2016-10-28
发明人： Biswajit Ray , Mohan Dunga , Changyuan Chen
CPC分类号： G11C16/3431 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/28 , G11C16/3418 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C16/3495
摘要： An erase operation includes one or more erase depth checks to detect the occurrence of shallow erased memory cells at the end of an erase process. Memory cells are subjected to erase and erase verification until erase verification success is achieved. At the end of successful erase verification, a subset of memory cells is read to detect an erase depth or level of the memory cells. If the erase depth check indicates that the subset memory cells are in a shallow erased condition, additional erasing and verification is performed.
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6.发明申请公开(公告)号：US20190035480A1
公开(公告)日：2019-01-31
申请号：US15699513
申请日：2017-09-08
发明人： Ching-Huang Lu , Anubhav Khandelwal , Changyuan Chen , Cynthia Hsu , Yingda Dong
摘要： Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.
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公开(公告)号：US10304551B2
公开(公告)日：2019-05-28
申请号：US15194295
申请日：2016-06-27
发明人： Biswajit Ray , Mohan Dunga , Gerrit Jan Hemink , Changyuan Chen
摘要： Apparatuses, systems, methods, and computer program products are disclosed for erase depth control. One apparatus includes a block of non-volatile storage cells. A controller is configured to perform a first erase operation on a block of non-volatile storage cells. A controller for a block is configured to determine a first set of storage cells of the block having a faster erase speed than a second set of storage cells of the block based on a verify voltage threshold. A controller for a block is configured to perform a second erase operation on the block using different voltages for a first set of storage cells and a second set of storage cells of the block.
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公开(公告)号：US10008273B2
公开(公告)日：2018-06-26
申请号：US15181346
申请日：2016-06-13
IPC分类号： G11C16/28 , G06F11/10 , G11C29/52 , G11C16/04 , G11C16/24 , G11C16/26 , G11C29/02 , G11C7/12 , G11C29/12
CPC分类号： G11C16/28 , G06F11/1068 , G11C7/12 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C29/028 , G11C29/52 , G11C2029/1204
摘要： Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.
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公开(公告)号：US09711231B1
公开(公告)日：2017-07-18
申请号：US15191898
申请日：2016-06-24
发明人： Chris Yip , Philip Reusswig , Nian Niles Yang , Grishma Shah , Abuzer Azo Dogan , Biswajit Ray , Mohan Dunga , Joanna Lai , Changyuan Chen
IPC分类号： G11C16/26 , G11C16/28 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/34 , G06F11/10 , G11C29/52
CPC分类号： G11C16/28 , G06F11/1048 , G11C11/5642 , G11C16/0483 , G11C16/30 , G11C16/32
摘要： Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. In one aspect, read voltages are set and optimized based on a time period since a last sensing operation. A timing device such as an n-bit digital counter may be provided for each block of memory cells to track the time. The counter is set to all 1's when the device is powered on. When a sensing operation occurs, the counter is periodically incremented based on a clock. When a next read operation occurs, the value of the counter is cross-referenced to an optimal set of read voltage shifts. Each block of cells may have its own counter, where the counters are incremented using a local or global clock.
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10.发明授权公开(公告)号：US09704588B1
公开(公告)日：2017-07-11
申请号：US15069287
申请日：2016-03-14
发明人： Biswajit Ray , Mohan Dunga , Changyuan Chen
CPC分类号： G11C16/26 , G11C7/04 , G11C7/062 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/20 , G11C16/344 , G11C2211/5621
摘要： Reduced errors when sensing non-volatile memory are provided by applying a current spike or preconditioning current for a group of memory cells included a selected cell. During a sense operation, a preconditioning current can be passed through a group of non-volatile memory cells. The preconditioning current is provided prior to applying at least one reference voltage to a selected word line. The preconditioning current may simulate a cell current passing through the channel during a verification phase of programming. The preconditioning current can modify a channel resistance to approximate a state during verification to provide a more stable threshold voltage for the memory cells. Preconditioning currents may be applied selectively for select reference levels, select pages, and/or select operations. Selective application of preconditioning currents based on temperature is also provided.
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