公开(公告)号：US11935599B2

公开(公告)日：2024-03-19

申请号：US17725911

申请日：2022-04-21

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  Fanglin Zhang ,  Victor Avila

IPC: G11C16/10 ,  G11C7/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/102 ,  G11C7/1051 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: A fast burst program sequence that reduces overall NAND flash programming time is disclosed. The burst program sequence includes maintaining a charge pump in an ON state and not fully discharging the WL/BLs at the conclusion of the programming phase of each program operation. As a result, the fast burst program sequence provides total program time savings over an existing cache program sequence by eliminating the full WL/BL discharge and charge pump reset that conventionally occurs after each program operation, which in turn, allows for the transfer of next page data from the page buffer to the data latches to be hidden within the program time of a prior/current program operation.

公开(公告)号：US11587630B2

公开(公告)日：2023-02-21

申请号：US17206865

申请日：2021-03-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Cynthia Hsu ,  Fanglin Zhang

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10

Abstract: A data storage system includes a storage medium including a plurality of strings of single-level cell (SLC) memory cells connected to a plurality of word lines; and a storage controller in communication with the storage medium, the storage controller including write circuitry configured to write data to the storage medium by: selecting a first word line of the plurality of word lines, the first word line being connected to a first plurality of strings; consecutively programming a first group of memory cells of the first plurality of strings connected to the first word line; and subsequent to programming the first group of memory cells, consecutively verifying respective programming results of the first group of memory cells.

公开(公告)号：US20220399061A1

公开(公告)日：2022-12-15

申请号：US17353298

申请日：2021-06-21

Applicant: SanDisk Technologies LLC

Inventor： Henry Chin ,  Hua-Ling Hsu ,  Liang Li ,  Xuan Tian ,  Fanglin Zhang ,  Guanhua Yin

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10

Abstract: Countermeasure method for programming a non-defective plane of a non-volatile memory experiencing a neighbor plane disturb, comprising, once a first plane is determined to have completed programming of a current state but where not all planes have completed the programming, a loop count is incremented and a determination is made as to whether the loop count exceeds a threshold. If so, programming of the incomplete plane(s) is ceased and programming of the completed plane(s) is resumed by suspending the loop count and bit scan mode, and, on a next program pulse, applying a pre-determined rollback voltage to decrement a program voltage bias. The loop count and bit scan mode are resumed once a threshold voltage level equals a program voltage bias when the loop count was last incremented. BSPF criterion is applied for each programmed state. Advancement to the next loop only occurs if a programmed state is determined incomplete.

公开(公告)号：US20220301644A1

公开(公告)日：2022-09-22

申请号：US17206865

申请日：2021-03-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Cynthia Hsu ,  Fanglin Zhang

IPC: G11C16/34 ,  G11C16/10

Abstract: A data storage system includes a storage medium including a plurality of strings of single-level cell (SLC) memory cells connected to a plurality of word lines; and a storage controller in communication with the storage medium, the storage controller including write circuitry configured to write data to the storage medium by: selecting a first word line of the plurality of word lines, the first word line being connected to a first plurality of strings; consecutively programming a first group of memory cells of the first plurality of strings connected to the first word line; and subsequent to programming the first group of memory cells, consecutively verifying respective programming results of the first group of memory cells.

公开(公告)号：US11361835B1

公开(公告)日：2022-06-14

申请号：US17188998

申请日：2021-03-01

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Fanglin Zhang ,  Huai-Yuan Tseng

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/08 ,  G11C16/30 ,  G11C16/26

Abstract: Apparatuses and techniques are described for avoiding current consumption peaks during a program operation for a memory device. The timing of scan operations of latches is adjusted to avoid overlapping with an increase in word line voltages. The scan operations can include a pre-charge select scan, which identifies memory cells subject to a verify test, and a fill operation for latches of memory cells which fail a verify test in a prior program loop. The pre-charge select scan can occur before the increase in the word line voltages, while the fill operation occurs after the increase in word line voltages. In another approach, the start of the increase in the word line voltages is delayed when a state bit scan is expected to take a relatively long time, e.g., when a verify test is passed in a prior program loop.