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公开(公告)号：US11705203B2
公开(公告)日：2023-07-18
申请号：US17352095
申请日：2021-06-18
Applicant: SanDisk Technologies LLC
Inventor： Henry Chin , Hua-Ling Cynthia Hsu , Wei Zhao , Fanglin Zhang
IPC: G11C16/00 , G11C16/14 , G11C16/26 , G11C16/34 , G06F1/20 , G11C16/04 , H01L25/065 , H10B43/10 , H10B43/27
CPC classification number: G11C16/14 , G06F1/20 , G11C16/26 , G11C16/3459 , G11C16/0483 , H01L25/0657 , H01L2225/06562 , H10B43/10 , H10B43/27
Abstract: Techniques disclosed herein cope with temperature effects in non-volatile memory systems. A control circuit is configured to sense a current temperature of the memory system and read, verify, program, and erase data in non-volatile memory cells by modifying one or more read/verify/program/erase parameters based on a temperature compensation value. The control circuit is further configured to read, verify, program, and erase data by accessing a historical temperature value stored in the memory system, the historical temperature value comprising a temperature at which a previous read, verify, program or erase occurred and measuring a current temperature value. The control circuit determines the temperature compensation value by applying a smoothing function. The smoothing function determines the temperature compensation value by selecting either the historical temperature value or the current temperature value as the temperature compensation value based on a difference between the historical temperature value and the current temperature relative to a threshold, or calculating the temperature compensation value, different from the current temperature value or the historical temperature value, based a smoothing function which utilizes the current temperature value and the historical temperature value.
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公开(公告)号：US11521686B2
公开(公告)日：2022-12-06
申请号：US17218498
申请日：2021-03-31
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Hua-Ling Hsu , Huai-Yuan Tseng , Fanglin Zhang
Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation. A control circuit is coupled to the word lines and the bit lines. The control circuit is configured to count a bit-scan quantity of the memory cells during a bit-scan of the program operation. The control circuit determines whether the bit-scan quantity of the plurality of memory cells is greater than at least one predetermined bit-scan threshold. In response to the bit-scan quantity of the memory cells being greater than the at least one predetermined bit-scan threshold, the control circuit is configured to adjust a word line ramp rate of a word line voltage applied to the word lines during the program operation.
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公开(公告)号：US20230350606A1
公开(公告)日：2023-11-02
申请号：US17732260
申请日：2022-04-28
Applicant: SanDisk Technologies LLC
Inventor： Hua-Ling Cynthia Hsu , Fanglin Zhang
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0679 , G06F13/1668
Abstract: A command/address sequence associated with a read/write operation for a memory device that utilizes an existing test data bus in a novel way that obviates the need to utilize an I/O bus for the command/address sequence. As such, the command/address sequence can be performed in parallel with the read/write operations, thereby removing a performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence detects a first enable signal and a data signal on the test data bus and decodes the data signal to obtain at least one of a command latch enable signal and address latch enable signal and at least one of a command code and an address code.
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公开(公告)号：US20220406383A1
公开(公告)日：2022-12-22
申请号：US17352095
申请日：2021-06-18
Applicant: SanDisk Technologies LLC
Inventor： Henry Chin , Hua-Ling Cynthia Hsu , Wei Zhao , Fanglin Zhang
Abstract: Techniques disclosed herein cope with temperature effects in non-volatile memory systems. A control circuit is configured to sense a current temperature of the memory system and read, verify, program, and erase data in non-volatile memory cells by modifying one or more read/verify/program/erase parameters based on a temperature compensation value. The control circuit is further configured to read, verify, program, and erase data by accessing a historical temperature value stored in the memory system, the historical temperature value comprising a temperature at which a previous read, verify, program or erase occurred and measuring a current temperature value. The control circuit determines the temperature compensation value by applying a smoothing function. The smoothing function determines the temperature compensation value by selecting either the historical temperature value or the current temperature value as the temperature compensation value based on a difference between the historical temperature value and the current temperature relative to a threshold, or calculating the temperature compensation value, different from the current temperature value or the historical temperature value, based a smoothing function which utilizes the current temperature value and the historical temperature value.
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公开(公告)号：US20220319605A1
公开(公告)日：2022-10-06
申请号：US17218498
申请日：2021-03-31
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Hua-Ling Hsu , Huai-Yuan Tseng , Fanglin Zhang
Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation. A control circuit is coupled to the word lines and the bit lines. The control circuit is configured to count a bit-scan quantity of the memory cells during a bit-scan of the program operation. The control circuit determines whether the bit-scan quantity of the plurality of memory cells is greater than at least one predetermined bit-scan threshold. In response to the bit-scan quantity of the memory cells being greater than the at least one predetermined bit-scan threshold, the control circuit is configured to adjust a word line ramp rate of a word line voltage applied to the word lines during the program operation.
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Patent Agency Ranking
公开(公告)号：US11355208B2
公开(公告)日：2022-06-07
申请号：US16916790
申请日：2020-06-30
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Fanglin Zhang , Zhuojie Li , Huai-Yuan Tseng
IPC: G11C16/06 , G11C16/34 , G11C16/04 , G11C16/10 , H01L27/11582 , G11C16/26 , H01L27/11565 , G11C11/56
Abstract: Apparatus and methods are described to program memory cells and verify stored values programmed into the cells. The next stage in stored memory can be moved to the current verification iteration when certain conditions are met. Verification can include counting bits that exceed a voltage value for a stage being verified to produce a bit count number and determining if the bit count number for the stage being verified meets a threshold value. If the bit count number does not meet the threshold, the verification process can continue with a current verify iteration and thereafter move to a next verify iteration. If the bit count number does meet the threshold, the process can add a next stage to the current verify iteration and thereafter move to a next verify iteration.
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7.发明授权公开(公告)号：US11605436B2
公开(公告)日：2023-03-14
申请号：US17353298
申请日：2021-06-21
Applicant: SanDisk Technologies LLC
Inventor： Henry Chin , Hua-Ling Hsu , Liang Li , Xuan Tian , Fanglin Zhang , Guanhua Yin
Abstract: Countermeasure method for programming a non-defective plane of a non-volatile memory experiencing a neighbor plane disturb, comprising, once a first plane is determined to have completed programming of a current state but where not all planes have completed the programming, a loop count is incremented and a determination is made as to whether the loop count exceeds a threshold. If so, programming of the incomplete plane(s) is ceased and programming of the completed plane(s) is resumed by suspending the loop count and bit scan mode, and, on a next program pulse, applying a pre-determined rollback voltage to decrement a program voltage bias. The loop count and bit scan mode are resumed once a threshold voltage level equals a program voltage bias when the loop count was last incremented. BSPF criterion is applied for each programmed state. Advancement to the next loop only occurs if a programmed state is determined incomplete.
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公开(公告)号：US20220392551A1
公开(公告)日：2022-12-08
申请号：US17336936
申请日：2021-06-02
Applicant: SanDisk Technologies LLC
Inventor： Hua-Ling Hsu , Henry Chin , Han-Ping Chen , Erika Penzo , Fanglin Zhang
Abstract: Apparatus and methods are described to program memory cells and control bit line discharge schemes during programming based on the data pattern. The memory controller can predict program data pattern based on SLC pulse number and TLC data completion signals and use these signals to adjust when the inhibited bit lines can discharge. Once a TLC program operation have more one data, the memory controller will enable EQVDDSA_PROG to equalize to VDDSA, and then discharge. In SLC program, the memory controller will enable EQVDDSA_PROG only in first program pulse and disable it thereafter.
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公开(公告)号：US11521691B1
公开(公告)日：2022-12-06
申请号：US17336936
申请日：2021-06-02
Applicant: SanDisk Technologies LLC
Inventor： Hua-Ling Hsu , Henry Chin , Han-Ping Chen , Erika Penzo , Fanglin Zhang
IPC: G11C16/04 , G11C16/34 , G11C16/10 , G11C16/24 , G11C11/56 , H01L27/11565 , G11C16/26 , H01L27/11582
Abstract: Apparatus and methods are described to program memory cells and control bit line discharge schemes during programming based on the data pattern. The memory controller can predict program data pattern based on SLC pulse number and TLC data completion signals and use these signals to adjust when the inhibited bit lines can discharge. Once a TLC program operation have more one data, the memory controller will enable EQVDDSA_PROG to equalize to VDDSA, and then discharge. In SLC program, the memory controller will enable EQVDDSA_PROG only in first program pulse and disable it thereafter.
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公开(公告)号：US12197783B2
公开(公告)日：2025-01-14
申请号：US17732260
申请日：2022-04-28
Applicant: SanDisk Technologies LLC
Inventor： Hua-Ling Cynthia Hsu , Fanglin Zhang
Abstract: A command/address sequence associated with a read/write operation for a memory device that utilizes an existing test data bus in a novel way that obviates the need to utilize an I/O bus for the command/address sequence. As such, the command/address sequence can be performed in parallel with the read/write operations, thereby removing a performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence detects a first enable signal and a data signal on the test data bus and decodes the data signal to obtain at least one of a command latch enable signal and address latch enable signal and at least one of a command code and an address code.
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