公开(公告)号：US12148710B2

公开(公告)日：2024-11-19

申请号：US17510807

申请日：2021-10-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Matsuno ,  Johann Alsmeier

IPC: H10B43/27 ,  H01L23/544 ,  H10B41/27

Abstract: A three-dimensional memory device includes a first alternating stack of first word lines and first insulating layers, first memory stack structures vertically extending through the first alternating stack, a second alternating stack of second word lines and second insulating layers, second memory stack structures vertically extending through the second alternating stack, plural backside trench fill structures located between the first alternating stack and the second alternating stack, and a bridge region located between the plural backside trench fill structures and between the between the first alternating stack and the second alternating stack. At least one insulating layer extends continuously through the first alternating stack, the second alternating stack, and the bridge region.

公开(公告)号：US20240178140A1

公开(公告)日：2024-05-30

申请号：US18221689

申请日：2023-07-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Matsuno ,  Kota Funayama

IPC: H01L23/528 ,  H01L23/522 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers having stepped surfaces in a contact region, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, at least one retro-stepped dielectric material portion overlying the alternating stack, finned dielectric pillar structures vertically extending through the alternating stack in the contact region, support pillar structures, and layer contact via structures vertically extending through the at least one retro-stepped dielectric material portion. Each of the layer contact via structures contacts a respective one of the electrically conductive layers and a respective one of the finned dielectric pillar structures.

公开(公告)号：US11587920B2

公开(公告)日：2023-02-21

申请号：US16936047

申请日：2020-07-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Johann Alsmeier ,  James Kai ,  Koichi Matsuno

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L27/11582 ,  H01L27/11556

Abstract: A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second alternating stack. The first electrically conductive layers have different lateral extents along the first horizontal direction that decrease with a respective vertical distance from driver circuit devices, and the second electrically conductive layers have different lateral extents along the first horizontal direction that increase with the respective vertical distance from the driver circuit devices.

公开(公告)号：US12243865B2

公开(公告)日：2025-03-04

申请号：US18100152

申请日：2023-01-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Johann Alsmeier ,  James Kai ,  Koichi Matsuno

IPC: H10B43/27 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B43/40 ,  H10B41/27

Abstract: A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second alternating stack. The first electrically conductive layers have different lateral extents along the first horizontal direction that decrease with a respective vertical distance from driver circuit devices, and the second electrically conductive layers have different lateral extents along the first horizontal direction that increase with the respective vertical distance from the driver circuit devices.

公开(公告)号：US11127729B2

公开(公告)日：2021-09-21

申请号：US16900098

申请日：2020-06-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Murshed Chowdhury ,  Koichi Matsuno ,  Johann Alsmeier

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A first wafer including a first substrate, first semiconductor devices overlying the first substrate, and first dielectric material layers overlying the first semiconductor devices is provided. A sacrificial material layer is formed over a top surface of a second wafer including a second substrate. Second semiconductor devices and second dielectric material layers are formed over a top surface of the sacrificial material layer. The second wafer is attached to the first wafer such that the second dielectric material layers face the first dielectric material layers. A plurality of voids is formed through the second substrate. The sacrificial material layer is removed by providing an etchant that etches a material of the sacrificial material layer through the plurality of voids. The substrate is detached from a bonded assembly including the first wafer, the second semiconductor devices, and the second dielectric material layers upon removal of the sacrificial material layer.

公开(公告)号：US12133388B2

公开(公告)日：2024-10-29

申请号：US17583456

申请日：2022-01-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kota Funayama ,  Satoshi Shimizu ,  Koichi Matsuno

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A memory device includes a lower source-level semiconductor layer, a source contact layer, an upper source-level semiconductor layer, and an alternating stack of insulating layers and electrically conductive layers, and a memory opening fill structure vertically extending through the alternating stack and down to an upper portion of the lower source-level semiconductor layer. The memory opening fill structure includes a vertical semiconductor channel, a memory film laterally surrounding the vertical semiconductor channel, and an annular semiconductor cap contacting a bottom surface of the memory film and contacting a top surface segment of the source contact layer. The annular semiconductor cap may be employed as an etch stop structure during a manufacturing process.

公开(公告)号：US12029036B2

公开(公告)日：2024-07-02

申请号：US17244258

申请日：2021-04-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenichi Shimomura ,  Koichi Matsuno ,  Johann Alsmeier

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: Two types of support pillar structures are formed in a staircase region of an alternating stack of insulating layers and sacrificial material layers. First-type support pillar structures are formed in areas distal from backside trenches to be subsequently formed, and second-type support pillar structures may be formed in areas proximal to the backside trenches. The second-type support pillar structures may be formed as dielectric support pillar structures, or may be formed with at least one additional dielectric spacer.

公开(公告)号：US20220352093A1

公开(公告)日：2022-11-03

申请号：US17806592

申请日：2022-06-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Katsuo Yamada ,  Kakeru Tamai ,  Akira Iwasaki ,  Akira Fukunaga ,  Koichi Matsuno

IPC: H01L23/00 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures located within a respective memory opening vertically extending through the alternating stack in a memory array region, and support pillar structures vertically extending through the alternating stack. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective memory film that contacts each layer within the alternating stack. Each of the support pillar structures includes a respective dummy vertical semiconductor channel, a respective dummy memory film, and at least one respective dielectric spacer material portion laterally surrounding the respective dummy memory film and interposed between the electrically conductive layers and the respective dummy memory film.

公开(公告)号：US10985169B2

公开(公告)日：2021-04-20

申请号：US16291577

申请日：2019-03-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Murshed Chowdhury ,  Koichi Matsuno ,  Johann Alsmeier

IPC: H01L27/11556 ,  H01L23/538 ,  H01L27/11582 ,  H01L23/532 ,  H01L27/1157 ,  H01L23/00 ,  H01L25/18 ,  H01L23/498 ,  H01L27/11524

Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.