公开(公告)号：US12004347B2

公开(公告)日：2024-06-04

申请号：US17237476

申请日：2021-04-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nobuyuki Fujimura ,  Satoshi Shimizu ,  Takumi Moriyama

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A plurality of arrays of memory opening fill structures is formed through the alternating stack. A plurality of dielectric plates is formed, which laterally surrounds a respective array of memory opening fill structures. Self-aligned drain-select-level isolation structures are formed between a respective neighboring pair of arrays of memory opening fill structures through gaps between neighboring pairs of the dielectric plates into a subset of layers within the alternating stack. Drain side select gate electrodes are provided from a divided subset of the spacer material layers.

公开(公告)号：US20200279861A1

公开(公告)日：2020-09-03

申请号：US16288656

申请日：2019-02-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya Uryu ,  Satoshi Shimizu ,  Nobuyuki Fujimura

IPC: H01L27/11582 ,  H01L25/065 ,  G11C5/06 ,  G11C16/08 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/1157 ,  H01L27/11573

Abstract: A bonded assembly includes a first memory die containing a first three-dimensional memory device, a second memory die containing a second three-dimensional memory device, and a support die bonded to the first memory die and comprising a peripheral circuitry configured to control the first three-dimensional memory device and the second three-dimensional memory device. The first memory die includes multiple rows of first-die proximal bonding pads, multiple rows of first-die distal bonding pads, and a plurality of first-die laterally-shifting electrically conductive paths connecting a respective one of the first-die proximal bonding pads and a respective one of the first-die distal bonding pads that is laterally offset from the respective one of the first-die proximal bonding pads. The first memory die and the second memory die can have an identical layout, and electrical connections can be shifted through the first memory die by the offset distance.

公开(公告)号：US20180122905A1

公开(公告)日：2018-05-03

申请号：US15458269

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Yasuo Kasagi ,  Satoshi Shimizu ,  Kazuyo Matsumoto ,  Yohei Masamori ,  Jixin Yu ,  Tong Zhang ,  James Kai

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.

公开(公告)号：US11127655B2

公开(公告)日：2021-09-21

申请号：US16295292

申请日：2019-03-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takumi Moriyama ,  Hiroshi Sasaki ,  Yohei Masamori ,  Satoshi Shimizu

IPC: H01L23/48 ,  H01L27/11582 ,  H01L27/11556 ,  H01L25/00 ,  H01L21/768 ,  H01L25/065

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. At least one dielectric material portion is formed over the substrate adjacent to the alternating stack. Memory stack structures are formed through the alternating stack. A trench extending through the alternating stack and a via cavity extending through the at least one dielectric material portion are formed using a same anisotropic etch process. The via cavity is deeper than the trench and the via cavity extends into an upper portion of the substrate. The sacrificial material layers are replaced with electrically conductive layers using the trench as a conduit for an etchant and a reactant. A trench fill structure is formed in the trench, and a via structure assembly is formed in the via cavity using simultaneous deposition of material portions. A bonding pad may be formed on the bottom surface of the via structure assembly.

公开(公告)号：US10957648B2

公开(公告)日：2021-03-23

申请号：US16432415

申请日：2019-06-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu-Hsien Hsu ,  Satoshi Shimizu ,  Shunsuke Akimoto

IPC: H01L27/11529 ,  H01L23/535 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/40 ,  H01L27/11524 ,  H01L29/06 ,  H01L27/1157

Abstract: A dielectric spacer assembly including an annular dielectric isolation structure is formed through in-process source-level material layers. An alternating stack of insulating layers and spacer material layers is formed over the in-process source-level material layers. A contact via cavity is formed through the dielectric spacer assembly, and is filled within a dielectric spacer and a sacrificial via fill structure. The dielectric spacer assembly protects the dielectric spacer during replacement of a source-level sacrificial layer with a source contact layer. The sacrificial via fill structure is subsequently replaced with a through-memory-level contact via structure.

公开(公告)号：US20200286815A1

公开(公告)日：2020-09-10

申请号：US16295292

申请日：2019-03-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takumi Moriyama ,  Hiroshi Sasaki ,  Yohei Masamori ,  Satoshi Shimizu

IPC: H01L23/48 ,  H01L27/11582 ,  H01L27/11556 ,  H01L25/065 ,  H01L21/768 ,  H01L25/00

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. At least one dielectric material portion is formed over the substrate adjacent to the alternating stack. Memory stack structures are formed through the alternating stack. A trench extending through the alternating stack and a via cavity extending through the at least one dielectric material portion are formed using a same anisotropic etch process. The via cavity is deeper than the trench and the via cavity extends into an upper portion of the substrate. The sacrificial material layers are replaced with electrically conductive layers using the trench as a conduit for an etchant and a reactant. A trench fill structure is formed in the trench, and a via structure assembly is formed in the via cavity using simultaneous deposition of material portions. A bonding pad may be formed on the bottom surface of the via structure assembly.

公开(公告)号：US20180366487A1

公开(公告)日：2018-12-20

申请号：US15720306

申请日：2017-09-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yasuchika Okizumi ,  Michiru Hirayama ,  Naoto Norizuki ,  Satoshi Shimizu ,  Yasuo Kasagi ,  Kimiaki Naruse

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/8234

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L21/823493 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578

Abstract: A method of forming a three-dimensional memory device includes forming at the least one lower level dielectric layer over a semiconductor substrate, forming a buried source line over the least one lower level dielectric layer and over the semiconductor substrate, such that the buried source line is electrically connected to the semiconductor substrate, forming an alternating stack of insulating layers and sacrificial material layers over the buried source line, such that the sacrificial material layers are subsequently replaced with, electrically conductive layers, forming memory openings through the alternating stack by etching through the alternating stack after the buried source line is electrically connected to the semiconductor substrate, and forming memory stack structures in the memory openings. Each memory stack structure includes a vertical semiconductor channel electrically connected to the buried source line and a memory film laterally surrounding the vertical semiconductor channel.

公开(公告)号：US10020363B2

公开(公告)日：2018-07-10

申请号：US15458269

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Yasuo Kasagi ,  Satoshi Shimizu ,  Kazuyo Matsumoto ,  Yohei Masamori ,  Jixin Yu ,  Tong Zhang ,  James Kai

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.

公开(公告)号：US12010835B2

公开(公告)日：2024-06-11

申请号：US17241321

申请日：2021-04-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Satoshi Shimizu

IPC: H10B41/27 ,  G11C8/14 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C8/14 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures vertically extending through the alternating stack in a memory array region, and an electrically conductive spacer extending vertically and electrically connecting a first drain-select-level electrically conductive layer to a second drain-select-level electrically conductive layer.

公开(公告)号：US11552100B2

公开(公告)日：2023-01-10

申请号：US16985340

申请日：2020-08-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Satoshi Shimizu ,  Yanli Zhang

IPC: H01L27/11582 ,  G11C8/14 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11565

Abstract: A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel. The vertical semiconductor channel has large grain sizes to provide high charge carrier mobility, and is free of or includes only a low concentration of carbon atoms and n-type dopants therein.