公开(公告)号：US11074976B2

公开(公告)日：2021-07-27

申请号：US16551553

申请日：2019-08-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani

IPC: G11C16/04 ,  G11C11/34 ,  G11C16/06 ,  G11C16/14 ,  G11C16/30 ,  H03H11/28 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/11556

Abstract: A memory system is provided with technology for performing temperature dependent impedance mitigation, in addition to or instead of other techniques to compensate for differences in impedance. For example, the memory system comprises a plurality of non-volatile memory cells, a first pathway connected to the plurality of non-volatile memory cells, a second pathway connected to the plurality of non-volatile memory cells, and a control circuit connected to the first pathway and the second pathway. The control circuit is configured to compensate based on temperature for a temperature dependent impedance mismatch between the first pathway and the second pathway during a memory operation on the plurality of non-volatile memory cells.

公开(公告)号：US11011209B2

公开(公告)日：2021-05-18

申请号：US16589404

申请日：2019-10-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jee-Yeon Kim ,  Kwang-Ho Kim ,  Yuki Mizutani ,  Fumiaki Toyama

IPC: H01L29/76 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519

Abstract: A semiconductor structure includes a memory die, which includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures vertically extending through the alternating stacks. A contact-level dielectric layer embeds drain contact via structures that are electrically connected to a respective drain region and contact-level metal interconnects, and a via-level dielectric embedding drain-to-bit-line connection via structures, bit-line-connection via structures, and pad-connection via structures. A bit-line-level dielectric layer overlies the via-level dielectric layer, and embeds bit lines that contact a respective subset of the drain-to-bit-line connection via structures, and embeds metal pads that contact a respective one of the pad-connection via structures. Each metal pad is electrically connected to a respective bit line through a series connection of a respective pad-connection via structure, a respective contact-level metal interconnect, and a respective bit-line-connection via structure.

公开(公告)号：US10923196B1

公开(公告)日：2021-02-16

申请号：US16781589

申请日：2020-02-04

Applicant: SanDisk Technologies LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/24 ,  H01L27/06 ,  G11C16/34

Abstract: An apparatus for erasing non-volatile storage elements in a non-volatile memory system is disclosed. The apparatus has consistent speed in gate induced drain leakage (GIDL) erase across the operating temperature of the memory system. In one aspect, a voltage source outputs an erase voltage to NAND strings. The NAND strings may draw a GIDL erase current in response to the erase voltage. The amount of GIDL erase current for a given erase voltage is highly temperature dependent. The GIDL erase current may be sampled, and the erase voltage regulated based on the GIDL erase current. Therefore, the GIDL erase current, as well as erase speed, may be kept uniform across operating temperatures.

公开(公告)号：US20200381316A1

公开(公告)日：2020-12-03

申请号：US16426984

申请日：2019-05-30

Applicant: SanDisk Technologies LLC

Inventor： Seungpil Lee ,  Kwang-Ho Kim

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/18 ,  H01L27/11582 ,  H01L25/00 ,  H01L21/78 ,  G01R31/02

Abstract: A first workpiece includes first active pads, a first test pad, and a second test pad on a primary surface of the first workpiece, the first test pad electrically connected to the second test pad. A second workpiece includes second active pads, a third test pad, and a fourth test pad on a primary surface of the second workpiece. The first and second workpieces are bonded along an interface between the primary surface of the first workpiece and the primary surface of the second workpiece to bond the first active pads with the second active pads, bond the first test pad with the third test pad, and bond the second test pad with the fourth test pad. Connectivity detection circuits test electrical connectivity between the third test pad and the fourth test pad

公开(公告)号：US10727215B1

公开(公告)日：2020-07-28

申请号：US16261869

申请日：2019-01-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Kwang-Ho Kim ,  Johann Alsmeier

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/04 ,  H01L25/065 ,  H01L27/11565 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  H01L27/11519

Abstract: A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.

公开(公告)号：US10650898B1

公开(公告)日：2020-05-12

申请号：US16182031

申请日：2018-11-06

Applicant: SanDisk Technologies LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani ,  Yingda Dong

IPC: G11C16/14 ,  G11C16/04 ,  H01L27/1157 ,  H01L27/11524

Abstract: An apparatus having an erase controller configured to perform a two-sided gate-induced drain leakage (GIDL) erase of non-volatile memory cells is disclosed. The erase controller is configured to apply a first voltage pulse having a first value for a voltage pulse attribute to the first end of a first pathway. The erase controller is configured to apply a second voltage pulse having a second value for the voltage pulse attribute to the first end of a second pathway. The first value and the second value are configured to compensate for different impedances such that a first erase voltage at a first select transistor is substantially symmetric with a second erase voltage at a second select transistor.

公开(公告)号：US11342244B2

公开(公告)日：2022-05-24

申请号：US16747943

申请日：2020-01-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jee-Yeon Kim ,  Kwang-Ho Kim ,  Fumiaki Toyama

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L23/00

Abstract: Through-substrate via structures are formed in a semiconductor substrate of a first semiconductor die. Semiconductor devices, dielectric material layers, and metal interconnect structures are formed over a front surface of the semiconductor substrate. A backside dielectric layer is formed on a backside surface. Integrated line and pad structures are formed over the backside dielectric layer on a respective through-substrate via structure. Each of the integrated line and pad structures includes a respective pad portion and respective line portion that extends from a center region of the backside surface to toward a periphery of the backside surface. A bonded assembly including the first semiconductor die and a second semiconductor die can be formed. Bonding pads can be provided in a center region of the interface between the semiconductor dies to facilitate power and signal distribution in the second semiconductor die with less electrical wiring.

公开(公告)号：US11133297B2

公开(公告)日：2021-09-28

申请号：US16669888

申请日：2019-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kwang-Ho Kim ,  Masaaki Higashitani ,  Fumiaki Toyama ,  Akio Nishida

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/00 ,  H01L27/11575 ,  H01L27/1157 ,  H01L23/48 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/522

Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.

公开(公告)号：US20210065802A1

公开(公告)日：2021-03-04

申请号：US16551553

申请日：2019-08-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani

IPC: G11C16/06 ,  G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  G11C16/30 ,  H03H11/28

Abstract: A memory system is provided with technology for performing temperature dependent impedance mitigation, in addition to or instead of other techniques to compensate for differences in impedance. For example, the memory system comprises a plurality of non-volatile memory cells, a first pathway connected to the plurality of non-volatile memory cells, a second pathway connected to the plurality of non-volatile memory cells, and a control circuit connected to the first pathway and the second pathway. The control circuit is configured to compensate based on temperature for a temperature dependent impedance mismatch between the first pathway and the second pathway during a memory operation on the plurality of non-volatile memory cells.

公开(公告)号：US20200143889A1

公开(公告)日：2020-05-07

申请号：US16233780

申请日：2018-12-27

Applicant: SanDisk Technologies LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani ,  Yingda Dong

IPC: G11C16/14 ,  G11C16/04 ,  H01L27/1157 ,  G11C16/34

Abstract: An apparatus comprising an impedance compensation circuit is disclosed. The impedance compensation circuit compensates for impedance differences between a first pathway connected to a first transistor and a second pathway connected to a second transistor. However, rather than making a compensation based on a signal (e.g., voltage) applied to either the first or the second pathway, a compensation is made based on the signals (e.g., voltage pulses) applied to third and fourth pathways connected to the transistors.