公开(公告)号：US12284807B2

公开(公告)日：2025-04-22

申请号：US17397777

申请日：2021-08-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Hardwell Chibvongodze ,  Zhixin Cui ,  Rajdeep Gautam

IPC: H10B43/27 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

公开(公告)号：US11889694B2

公开(公告)日：2024-01-30

申请号：US17397846

申请日：2021-08-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Zhixin Cui ,  Rajdeep Gautam ,  Hiroyuki Ogawa

IPC: G11C11/34 ,  H10B43/27 ,  G11C5/06 ,  H01L23/522 ,  G11C8/14 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35

CPC classification number: H10B43/27 ,  G11C5/063 ,  G11C8/14 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/35

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

公开(公告)号：US11335671B2

公开(公告)日：2022-05-17

申请号：US16886164

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Zhixin Cui ,  Rajdeep Gautam

IPC: H01L25/18 ,  H01L23/00 ,  G11C7/12 ,  H01L25/00 ,  G11C7/06

Abstract: Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.

公开(公告)号：US11069410B1

公开(公告)日：2021-07-20

申请号：US16985335

申请日：2020-08-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Hardwell Chibvongodze ,  Rajdeep Gautam

IPC: G11C16/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11597 ,  G11C17/16 ,  G11C17/18 ,  G11C16/04 ,  G11C16/26 ,  G11C11/22 ,  H01L27/112

Abstract: First alternating stacks of first insulating strips and first spacer material strips is formed in a first device region, second alternating stacks of second insulating strips and second spacer material strips are formed in a second device region. Each of the first line trenches is filled with a respective laterally alternating sequence of memory stack structures and first dielectric pillar structures to form a three-dimensional NAND memory. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements. Each of the second line trenches with a respective laterally alternating sequence of active region assemblies of lateral field effect transistors and second dielectric pillar structures to form a three-dimensional NOR memory. Each of the active region assemblies includes a source pillar, a drain pillar, and a tubular channel region. The spacer material strips include, or are subsequently replaced with, electrically conductive strips.

公开(公告)号：US10971231B1

公开(公告)日：2021-04-06

申请号：US16912720

申请日：2020-06-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rajdeep Gautam ,  Hardwell Chibvongodze ,  Ken Oowada

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/28

Abstract: Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.

公开(公告)号：US20190252029A1

公开(公告)日：2019-08-15

申请号：US15897550

申请日：2018-02-15

Applicant: SanDisk Technologies LLC

Inventor： Chun-Hung Lai ,  Rajdeep Gautam ,  Ching-Huang Lu ,  Shih-Chung Lee

IPC: G11C16/34 ,  G11C16/16 ,  G11C7/14 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/3445 ,  G11C7/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16

Abstract: Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a dummy memory cell adjacent to a select gate transistor is weakly programmed during an erase operation by applying a program pulse to the dummy memory cell. The program pulse can be applied after an erase bias is applied to the memory cells and before an erase-verify test is performed, in one approach. The program pulse can be applied during the setup of the voltages for the erase-verify test. The magnitude of the program pulse can be increased in successive erase loops of an erase operation as the magnitude of a substrate voltage is also increased. The magnitude of the program pulse can also be set as an increasing function of a number of program-erase (P-E) cycles.