公开(公告)号：US20190393119A1

公开(公告)日：2019-12-26

申请号：US16016712

申请日：2018-06-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Maria Cristina ESTACIO ,  Elsie Agdon CABAHUG ,  Romel N. MANATAD

IPC: H01L23/367 ,  H01L23/29 ,  H01L23/495

Abstract: In a general aspect, a packaged semiconductor device apparatus a conductive paddle, a semiconductor die coupled with the conductive paddle and a conductive clip having a first portion with a first thickness and a second portion with a second thickness. The first thickness can be greater than the second thickness. The first portion can be coupled with the semiconductor die. The device can also include a molding compound encapsulating the semiconductor die and at least partially encapsulating the conductive paddle and the conductive clip. The device can further include a signal lead that is at least partially encapsulated in the molding compound, the second portion of the conductive clip being coupled with the signal lead.

公开(公告)号：US20240363471A1

公开(公告)日：2024-10-31

申请号：US18755366

申请日：2024-06-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Maria Cristina ESTACIO ,  Elsie Agdon CABAHUG ,  Romel N. MANATAD

IPC: H01L23/367 ,  H01L23/29 ,  H01L23/495

CPC classification number: H01L23/367 ,  H01L23/29 ,  H01L23/49517 ,  H01L23/49562 ,  H01L23/49575

Abstract: In a general aspect, a packaged semiconductor device apparatus a conductive paddle, a semiconductor die coupled with the conductive paddle and a conductive clip having a first portion with a first thickness and a second portion with a second thickness. The first thickness can be greater than the second thickness. The first portion can be coupled with the semiconductor die. The device can also include a molding compound encapsulating the semiconductor die and at least partially encapsulating the conductive paddle and the conductive clip. The device can further include a signal lead that is at least partially encapsulated in the molding compound, the second portion of the conductive clip being coupled with the signal lead.

公开(公告)号：US20240258268A1

公开(公告)日：2024-08-01

申请号：US18632548

申请日：2024-04-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Inpil YOO ,  Maria Cristina ESTACIO ,  Jerome TEYSSEYRE ,  Seungwon IM ,  JooYang EOM

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/52

CPC classification number: H01L24/92 ,  H01L21/56 ,  H01L23/49527 ,  H01L23/49575 ,  H01L23/52 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/40 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/84 ,  H01L23/3107 ,  H01L23/49513 ,  H01L2224/24011 ,  H01L2224/24101 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/40101 ,  H01L2224/40137 ,  H01L2224/73213 ,  H01L2224/73217 ,  H01L2224/73263 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/8384 ,  H01L2224/8484 ,  H01L2224/92142 ,  H01L2224/92144

Abstract: Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.

公开(公告)号：US20230402350A1

公开(公告)日：2023-12-14

申请号：US18454970

申请日：2023-08-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Erwin Ian Vamenta ALMAGRO ,  Maria Clemens Ypil QUINONES ,  Romel N. MANATAD ,  Maria Cristina ESTACIO ,  Elsie Agdon CABAHUG

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L23/49541 ,  H01L23/31 ,  H01L23/5226

Abstract: Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).

公开(公告)号：US20230207411A1

公开(公告)日：2023-06-29

申请号：US18172641

申请日：2023-02-22

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Maria Cristina ESTACIO ,  Jerome TEYSSEYRE ,  Elsie Agdon CABAHUG

IPC: H01L23/31 ,  H01L29/16 ,  H01L23/00 ,  H01L21/56 ,  H01L23/367 ,  H01L23/495

CPC classification number: H01L23/3107 ,  H01L29/1608 ,  H01L24/09 ,  H01L21/565 ,  H01L23/367 ,  H01L23/49524 ,  H01L23/49582 ,  H01L2224/02379

Abstract: A semiconductor package is disclosed. Specific implementations of a semiconductor package may include: one or more semiconductor die coupled between a baseframe and a clip, the baseframe including a gate pad of the baseframe coupled with a gate pad of the one or more semiconductor die, and a source pad of the baseframe coupled with a source pad of the one or more semiconductor die, where the gate pad of the baseframe extends beyond a perimeter of the one or more semiconductor die.

公开(公告)号：US20230075519A1

公开(公告)日：2023-03-09

申请号：US18055139

申请日：2022-11-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Maria Cristina ESTACIO ,  Seungwon IM

IPC: H01L23/495 ,  H01L23/00 ,  H01L29/16 ,  H01L23/473 ,  H01L23/433 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56

Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.

公开(公告)号：US20190122970A1

公开(公告)日：2019-04-25

申请号：US15789254

申请日：2017-10-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Maria Cristina ESTACIO ,  Seungwon IM

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L29/16

Abstract: In a general aspect, an apparatus can include a package including a common gate conductor, a first silicon carbide die having a die gate conductor, and a second silicon carbide die having a die gate conductor. The apparatus can include a first conductive path between the common gate conductor and the die gate conductor of the first silicon carbide die and a second conductive path between the common gate conductor and the die gate conductor of the second silicon carbide die where the first conductive path has a length substantially equal to a length of the second conductive path.