公开(公告)号：US20120061774A1

公开(公告)日：2012-03-15

申请号：US13299471

申请日：2011-11-18

申请人： Yusuke Morita ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Nobuyuki Sugii ,  Shinichiro Kimura

发明人： Yusuke Morita ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Nobuyuki Sugii ,  Shinichiro Kimura

IPC分类号： H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/823828 ,  H01L21/823864

摘要： Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.

摘要翻译： 提高了具有MIS晶体管的半导体器件的性能。 半导体器件包括：一对源极/漏极区域，每个源极/漏极区域通过在硅衬底的主表面上层叠半导体层而形成; 覆盖源极/漏极区域的每个侧壁的侧壁绝缘膜; 栅电极，被布置成在平面内被所述侧壁绝缘膜夹持的位置处在所述硅衬底的主表面上插入栅极绝缘膜; 以及延伸区域，其形成为从栅极电极下方和横向的部分延伸到每个源极/漏极区域的下方和侧面的部分，其中侧壁绝缘膜的侧壁与栅极绝缘膜和栅极电极相邻 具有向前锥形的倾斜。

公开(公告)号：US20120018807A1

公开(公告)日：2012-01-26

申请号：US13145108

申请日：2010-01-18

申请人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

发明人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

IPC分类号： H01L27/12 ,  B82Y99/00

CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/78648

摘要： In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.

摘要翻译： 在以高功率低功耗工作的SOI-MISFET中，元件面积减小。 虽然SOI型MISFET的N导电型MISFET区域的扩散层区域和SOI型MISFET的P导电型MISFET区域的扩散层区域形成为公共区域，但是施加衬底电位的阱扩散层 通过STI层将N导电型MISFET区域和P导电型MISFET区域相互分离。 位于N和P导电型MISFET区域中的扩散层区域）作为CMISFET的输出部分形成为公共区域，并通过硅化金属直接连接，使元件面积减小。

公开(公告)号：US08643117B2

公开(公告)日：2014-02-04

申请号：US13145108

申请日：2010-01-18

申请人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

发明人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

IPC分类号： H01L21/70

CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/78648

摘要： In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.

摘要翻译： 在以高功率低功耗工作的SOI-MISFET中，元件面积减小。 虽然SOI型MISFET的N导电型MISFET区域的扩散层区域和SOI型MISFET的P导电型MISFET区域的扩散层区域形成为公共区域，但是施加衬底电位的阱扩散层 通过STI层将N导电型MISFET区域和P导电型MISFET区域相互分离。 位于N和P导电型MISFET区域中的扩散层区域）作为CMISFET的输出部分形成为公共区域，并通过硅化金属直接连接，使元件面积减小。

公开(公告)号：US20090096036A1

公开(公告)日：2009-04-16

申请号：US12248250

申请日：2008-10-09

申请人： Takashi ISHIGAKI ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

发明人： Takashi ISHIGAKI ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/76283 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207

摘要： There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

摘要翻译： 提供了SOI-MISFET，其包括：SOI层; 设置在插入栅极绝缘体的SOI层上的栅电极; 以及第一升高层，其在SOI层上的栅电极的两个侧壁侧的SOI层高于栅电极，从而构成源极和漏极。 此外，还提供了一种体MISFET，包括：设置在硅衬底上的栅电极，其插入比SOI MISFET的栅极绝缘体更厚的栅极绝缘体; 以及构造在栅电极的两个侧壁处设置在半导体衬底上的源极和漏极的第二升高层。 第一升高层比升高的层厚，并且整个栅电极，SOI-MISFET的源极和漏极的一部分以及体MISFET的源极和漏极的一部分被硅化。

公开(公告)号：US08350328B2

公开(公告)日：2013-01-08

申请号：US12759559

申请日：2010-04-13

申请人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii

发明人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Characteristics of a semiconductor device having a FINFET are improved. The FINFET has: a channel layer arranged in an arch shape on a semiconductor substrate and formed of monocrystalline silicon; a front gate electrode formed on a part of an outside of the channel layer through a front gate insulating film; and a back gate electrode formed so as to be buried inside the channel layer through a back gate insulating film. The back gate electrode arranged inside the arch shape is arranged so as to pass through the front gate electrode.

摘要翻译： 具有FINFET的半导体器件的特性得到改善。 FINFET具有：在半导体衬底上以拱形形式布置并由单晶硅形成的沟道层; 前栅电极，其通过前栅极绝缘膜形成在沟道层的外部的一部分上; 以及形成为通过背栅绝缘膜埋设在沟道层内的背栅电极。 布置在拱形内侧的背栅极布置成穿过前栅电极。

公开(公告)号：US08183115B2

公开(公告)日：2012-05-22

申请号：US13088020

申请日：2011-04-15

申请人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

发明人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

IPC分类号： H01L21/8234

CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/76283 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207

摘要： There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. The first elevated layer is thicker than the second elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

摘要翻译： 提供了SOI-MISFET，其包括：SOI层; 设置在插入栅极绝缘体的SOI层上的栅电极; 以及第一升高层，其在SOI层上的栅电极的两个侧壁侧的SOI层高于栅电极，从而构成源极和漏极。 此外，还提供了一种体MISFET，包括：设置在硅衬底上的栅电极，其插入比SOI MISFET的栅极绝缘体更厚的栅极绝缘体; 以及构造在所述栅电极的两个侧壁处设置在半导体衬底上的源极和漏极的第二升高层。 第一升高层比第二升高层厚，并且整个栅电极，SOI-MISFET的源极和漏极的一部分以及体MISFET的源极和漏极的一部分被硅化。

公开(公告)号：US20100258869A1

公开(公告)日：2010-10-14

申请号：US12757090

申请日：2010-04-09

申请人： Yusuke MORITA ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Hiroyuki Yoshimoto ,  Nobuyuki Sugii ,  Shinichiro Kimura

发明人： Yusuke MORITA ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Hiroyuki Yoshimoto ,  Nobuyuki Sugii ,  Shinichiro Kimura

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： An n well and a p well disposed at a predetermined interval on a main surface of a SOI substrate with a thin BOX layer are formed, and an nMIS formed on the p well has a pair of n-type source/drain regions formed on semiconductor layers stacked on a main surface of the SOI layer at a predetermined distance, a gate insulating film, a gate electrode and sidewalls sandwiched between the pair of n-type source/drain regions. A device isolation is formed between the n well and the p well, and a side edge portion of the device isolation extends toward a gate electrode side more than a side edge portion of the n-type source/drain region (sidewall of the BOX layer).

摘要翻译： 形成在具有薄BOX层的SOI衬底的主表面上以预定间隔布置的n阱和p阱，并且在p阱上形成的nMIS具有形成在半导体层上的一对n型源极/漏极区 堆叠在SOI层的主表面上，预定距离处，栅极绝缘膜，栅电极和夹在该对n型源极/漏极区之间的侧壁。 在n阱和p阱之间形成器件隔离，并且器件隔离的侧边缘部分比n型源极/漏极区域的侧边缘部分（BOX层的侧壁）朝向栅电极侧延伸 ）。

公开(公告)号：US20070290264A1

公开(公告)日：2007-12-20

申请号：US11674420

申请日：2007-02-13

申请人： Nobuyuki Sugii ,  Ryuta Tsuchiya ,  Yusuke Morita

发明人： Nobuyuki Sugii ,  Ryuta Tsuchiya ,  Yusuke Morita

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7846 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/78654

摘要： The invention aims at increasing an effect of a strain applying technique for enhancing transistor performance in a fully depleted silicon-on-insulator (FDSOI) type transistor having a thin buried oxide (BOX) film. In an FDSOI type transistor having a very thin SOI structure (6), a stress generating region is formed on a back face side (5) of a very thin BOX layer (4) in order to apply strains to portions in which channels are intended to be formed. Desired portions on a back face side of the BOX layer (4) are amorphized by performing ion implantation, and are then recrystallized by performing a heat treatment in a state where a stress applying film (3) is formed, thereby transferring stresses from the stress applying film (3) to the portions in which the channels are intended to be formed. Thus, the stress generating region is formed.

摘要翻译： 本发明的目的在于增加在具有薄的掩埋氧化物（BOX）膜的完全耗尽的绝缘体上绝缘体（FDSOI）型晶体管中增强晶体管性能的应变施加技术的效果。 在具有非常薄的SOI结构（6）的FDSOI型晶体管中，在非常薄的BOX层（4）的背面（5）上形成应力产生区域，以便将应变施加到通道所在的部分 要形成 BOX层（4）的背面侧的期望部分通过进行离子注入而非晶化，然后在形成应力施加膜（3）的状态下进行热处理，从而从应力传递应力 将膜（3）施加到要形成通道的部分。 因此，形成应力产生区域。

公开(公告)号：US20060073664A1

公开(公告)日：2006-04-06

申请号：US11242961

申请日：2005-10-05

申请人： Masao Kondo ,  Nobuyuki Sugii ,  Yoshinobu Kimura

发明人： Masao Kondo ,  Nobuyuki Sugii ,  Yoshinobu Kimura

IPC分类号： H01L21/336

CPC分类号： H01L29/7835 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66659

摘要： Provided is a technology capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A p type strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The p type strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the p type strained silicon layer and p type silicon-germanium layer. At a position which is below the end of a gate electrode and at which misfit dislocations occur, the impurity concentration of the n type strained silicon layer and n type silicon-germanium layer is 1×1019 cm−3 or less.

摘要翻译： 提供了能够抑制形成在应变硅层中的沟道区域中的电子迁移率降低的技术。 在半导体衬底上形成的p型硅 - 锗层上形成p型应变硅层。 p型应变层的厚度被调整为比没有失配位错发生的临界膜厚度更厚。 因此，在p型应变硅层和p型硅 - 锗层之间的界面附近发生失配位错。 在位于栅电极末端并发生失配位错的位置处，n型应变硅层和n型硅 - 锗层的杂质浓度为1×10 19 cm -3， -3以下。

公开(公告)号：US07944024B2

公开(公告)日：2011-05-17

申请号：US12894609

申请日：2010-09-30

申请人： Masao Kondo ,  Nobuyuki Sugii ,  Yoshinobu Kimura

发明人： Masao Kondo ,  Nobuyuki Sugii ,  Yoshinobu Kimura

IPC分类号： H01L31/117

CPC分类号： H01L29/7835 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66659

摘要： A semiconductor device is provided which is capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the strained silicon layer and silicon-germanium layer.

摘要翻译： 提供一种半导体器件，其能够抑制在应变硅层中形成的沟道区域中的电子迁移率的降低。 在半导体衬底上形成的p型硅 - 锗层上形成应变硅层。 应变层的厚度被调整为比不发生失配位错的临界膜厚度更厚。 因此，失配位错发生在应变硅层和硅 - 锗层之间的界面附近。