公开(公告)号：US10339080B2

公开(公告)日：2019-07-02

申请号：US15188347

申请日：2016-06-21

Applicant: SK hynix Inc.

Inventor： Hyung-Gyun Yang ,  Yong-Ju Kim ,  Yong-Kee Kwon ,  Hong-Sik Kim

IPC: G06F13/28 ,  G06F12/02 ,  G06F13/42 ,  G11C7/10

Abstract: A system includes a central processing unit (CPU); main and auxiliary storage devices coupled to a plurality of memory ports; a memory bus suitable for coupling the CPU and the plurality of memory ports; and a memory controller suitable for, when the CPU calls data stored in the auxiliary storage device, controlling the called data to be transferred from the auxiliary storage device to the main storage device and stored in the main storage device.

公开(公告)号：US09792065B2

公开(公告)日：2017-10-17

申请号：US14885902

申请日：2015-10-16

Applicant: SK hynix Inc. ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Won-Gyu Shin ,  Jung-Whan Choi ,  Lee-Sup Kim ,  Young-Suk Moon ,  Yong-Kee Kwon

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/123

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/0215 ,  G06F12/123

Abstract: A memory controller schedules requests to memory devices according to scores. For this purpose, the memory controller variably adjusts weights for determining the scores with respect to the requests, calculates the scores using the weights, and determines a processing order of the requests according to the scores. The memory controller includes a request queue, a scheduler, and a weight generation circuit. The request queue stores the requests provided from an external device. The scheduler calculates a score for each request included in the request queue and determines the processing order of the requests based on the scores for the requests. The weight generation circuit generates a weight vector including the weights used to calculate the scores.

公开(公告)号：US20170017410A1

公开(公告)日：2017-01-19

申请号：US14981387

申请日：2015-12-28

Applicant: SK hynix Inc.

Inventor： Jong-Bum Park ,  Yong-Kee Kwon ,  Yong-Ju Kim

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0688

Abstract: A memory controller includes: a write performance storage circuit suitable for storing write performance indexes of physical memory areas of a memory device, a write counting circuit suitable for counting a number of requests of a write operation on logical memory areas of the memory device, and a mapping circuit suitable for mapping a logical memory area, for which the number of requests of the write operation r may be relatively large, to a physical memory area with a better write performance index.

Abstract translation: 存储器控制器包括：写入性能存储电路，适用于存储存储器件的物理存储器区域的写入性能指标;写入计数电路，用于对存储器件的逻辑存储器区域上的写入操作的数量进行计数;以及 适于将写入操作r的请求数量可能相对较大的逻辑存储器区域映射到具有更好的写入性能指数的物理存储器区域的映射电路。

公开(公告)号：US09304854B2

公开(公告)日：2016-04-05

申请号：US13908543

申请日：2013-06-03

Applicant: SK hynix Inc.

Inventor： Young-Suk Moon ,  Hyung-Dong Lee ,  Yong-Kee Kwon ,  Hong-Sik Kim ,  Hyung-Gyun Yang ,  Joon-Woo Kim

IPC: G06F11/10 ,  G06F11/20 ,  G06F11/14 ,  G06F11/16 ,  G11C29/04

CPC classification number: G06F11/1024 ,  G06F11/1048 ,  G06F11/141 ,  G06F11/1666 ,  G06F11/2094 ,  G11C2029/0411

Abstract: A semiconductor device includes a controller configured to receive a request for a first memory device, determine whether or not a multi-bit error has occurred at a requested address of the first memory device, and process the request on a second memory device instead of the first memory device, when the multi-bit error has occurred.

Abstract translation: 半导体器件包括：控制器，被配置为接收对第一存储器件的请求，确定在第一存储器件的请求地址是否发生了多位错误，并且在第二存储器件上处理该请求，而不是 第一个存储器件，当发生多位错误时。

公开(公告)号：US09245600B2

公开(公告)日：2016-01-26

申请号：US13913058

申请日：2013-06-07

Applicant: SK hynix Inc.

Inventor： Young-Suk Moon ,  Yong-Kee Kwon ,  Hong-Sik Kim

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1039 ,  G06F13/385 ,  G11C7/22

Abstract: A semiconductor device comprises: a read queue configured to store one or more read requests to a semiconductor memory device; a write queue configured to store one or more write requests to the semiconductor memory device; and a dispatch block configured to determine a scheduling order of the one or more read requests and the one or more write requests and switch to the read queue or to the write queue if a request exists in a Row Hit state in the read queue or in the write queue.

Abstract translation: 半导体器件包括：读队列，被配置为将一个或多个读请求存储到半导体存储器件; 写入队列，被配置为将一个或多个写入请求存储到所述半导体存储器件; 以及调度块，被配置成确定所述一个或多个读取请求和所述一个或多个写入请求的调度顺序，并且如果请求存在于所述读取队列中的行命中状态中，则切换到所述读取队列或所述写入队列 写队列。

公开(公告)号：US09135134B2

公开(公告)日：2015-09-15

申请号：US13908733

申请日：2013-06-03

Applicant: SK hynix Inc.

Inventor： Young-Suk Moon ,  Hyung-Dong Lee ,  Yong-Kee Kwon ,  Hong-Sik Kim

IPC: G06F11/00 ,  G06F11/30 ,  G06F12/00 ,  G06F12/08 ,  G06F11/07 ,  G11C7/02 ,  G11C11/406 ,  G11C11/408

CPC classification number: G06F11/3037 ,  G06F11/004 ,  G06F11/073 ,  G06F12/00 ,  G06F12/0804 ,  G11C7/02 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40618 ,  G11C11/408

Abstract: A semiconductor device includes a controller configured to control a first memory device to process a request for the first memory device. The controller receives the request for the first memory device, determines a data damage risk of cells connected to one or more second signal lines adjacent to a first signal line of the first memory device corresponding to a requested address by referring to information indicating a data damage risk, and restore data in one or more cells of the cells connected to the second signal line when determining that there is the data damage risk.

Abstract translation: 半导体器件包括被配置为控制第一存储器件以处理对第一存储器件的请求的控制器。 控制器接收对第一存储器件的请求，通过参考指示数据损坏的信息来确定连接到与所请求的地址相对应的与第一存储器件的第一信号线相邻的一个或多个第二信号线的单元的数据损坏风险 风险，并且在确定存在数据损害风险时恢复连接到第二信号线的单元的一个或多个单元中的数据。