公开(公告)号：US20230290785A1

公开(公告)日：2023-09-14

申请号：US18319912

申请日：2023-05-18

Applicant: Socionext Inc.

Inventor： Toshio HINO

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11881

Abstract: In a semiconductor integrated circuit device, a cell having no logical function placed in an end row of a plurality of cell rows includes: a third transistor opposed to a transistor of a cell adjacent in the Y direction; a third buried power line supplying VSS placed on the same side of the third transistor as the transistor of the adjacent cell; and a fourth buried power line supplying VDD placed on the opposite side of the third transistor from the transistor of the adjacent cell. The fourth buried power line is greater in size in the Y direction than the third buried power line.

公开(公告)号：US20230163133A1

公开(公告)日：2023-05-25

申请号：US18150501

申请日：2023-01-05

Applicant: SOCIONEXT INC.

Inventor： Toshio HINO ,  Junji IWAHORI

IPC: H01L27/118 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/06 ,  H01L27/092 ,  H01L29/786 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L29/4238 ,  H01L29/1079 ,  H01L21/823828 ,  H01L29/775 ,  H01L29/0847 ,  B82Y10/00 ,  H01L29/42392 ,  H01L21/823821 ,  H01L29/0696 ,  H01L29/0673 ,  H01L27/0924 ,  H01L29/78696 ,  H01L27/0207 ,  H01L2027/11864 ,  H01L2027/11874

Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

公开(公告)号：US20220336499A1

公开(公告)日：2022-10-20

申请号：US17719052

申请日：2022-04-12

Applicant: Socionext Inc.

Inventor： Hideyuki KOMURO ,  Toshio HINO ,  Tomoya TSURUTA

IPC: H01L27/118

Abstract: In a power line structure for supplying power to standard cells, buried power lines extending in the X direction are placed at a given spacing in the Y direction. A local power line extending in the Y direction is connected with the buried power lines. Metal power lines extending in the X direction are formed in an upper-layer metal interconnect layer and connected with the local power line. The spacing of placement of the metal power lines in the Y direction is greater than the spacing of placement of the buried power lines.

公开(公告)号：US20220310658A1

公开(公告)日：2022-09-29

申请号：US17838895

申请日：2022-06-13

Applicant: SOCIONEXT INC.

Inventor： Toshio HINO ,  Junji IWAHORI

IPC: H01L27/118 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L27/02

Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

公开(公告)号：US20220231053A1

公开(公告)日：2022-07-21

申请号：US17577994

申请日：2022-01-18

Applicant: Socionext Inc.

Inventor： Hirotaka TAKENO ,  Atsushi OKAMOTO ,  Toshio HINO

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes first and second power supply lines formed in a first wiring layer and extending in a first direction; third and fourth power supply lines formed in a second wiring layer, extending in a second direction, and connected to the first and second power supply lines, respectively; a fifth power supply line formed in the first wiring layer; and a first power switch circuit including a transistor provided between the first and fifth power supply lines. The transistor overlaps at least one of the third and fourth power supply lines. The first power switch circuit includes first and second wirings formed in the second wiring layer, extending in the second direction, not overlapping the third and fourth power supply lines, and connected to a source of the transistor and the fifth power supply line, and to a drain and the third power supply line, respectively.