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    Package with interlocking leads and manufacturing the same
    12.
    发明授权
    Package with interlocking leads and manufacturing the same 有权

    公开(公告)号：US10529672B2

    公开(公告)日：2020-01-07

    申请号：US15693277

    申请日：2017-08-31

    Applicant: STMicroelectronics, Inc.

    Inventor： Aaron Cadag ,  Lester Joseph Belalo ,  Ela Mia Cadag

    IPC: H01L21/56 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/78

    Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame. This differential in height reduces the span of wires used to form electrical connections within the semiconductor package. These reductions in the span of the wires reduces the chances of wire to wire and wire to die short circuiting because the wire sweep of the wires is reduced when the molding compound is placed.

    Bottom package exposed die MEMS pressure sensor integrated circuit package design
    13.
    发明授权
    Bottom package exposed die MEMS pressure sensor integrated circuit package design 有权

    公开(公告)号：US10483191B2

    公开(公告)日：2019-11-19

    申请号：US15212107

    申请日：2016-07-15

    Applicant: STMicroelectronics, Inc.

    Inventor： Aaron Cadag ,  Frederick Arellano ,  Ernesto Antilano, Jr.

    IPC: B81B7/00 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  B81C1/00

    Abstract: A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound.

    Lead stabilization in semiconductor packages
    15.
    发明授权
    Lead stabilization in semiconductor packages 有权

    公开(公告)号：US12211774B2

    公开(公告)日：2025-01-28

    申请号：US16848635

    申请日：2020-04-14

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Ela Mia Cadag ,  Frederick Ray Gomez ,  Aaron Cadag

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

    Abstract: Generally described, one or more embodiments are directed to semiconductor packages comprising a plurality of leads and methods of forming same. The plurality of leads include active leads that are electrically coupled to bond pads of a semiconductor die and thereby coupled to active components of the semiconductor die, and inactive leads that are not electrically coupled to bond pads of the semiconductor die. The active leads have surfaces that are exposed at a lower surface of the semiconductor package and forms lands, while the inactive leads are not exposed at the lower surface of the package.

    Package with interlocking leads and manufacturing the same
    16.
    发明授权
    Package with interlocking leads and manufacturing the same 有权

    公开(公告)号：US11557548B2

    公开(公告)日：2023-01-17

    申请号：US17137262

    申请日：2020-12-29

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Aaron Cadag ,  Lester Joseph Belalo ,  Ela Mia Cadag

    IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

    Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame. This differential in height reduces the span of wires used to form electrical connections within the semiconductor package. These reductions in the span of the wires reduces the chances of wire to wire and wire to die short circuiting because the wire sweep of the wires is reduced when the molding compound is placed.

    PACKAGE WITH INTERLOCKING LEADS AND MANUFACTURING THE SAME
    17.
    发明申请
    PACKAGE WITH INTERLOCKING LEADS AND MANUFACTURING THE SAME 有权

    公开(公告)号：US20210118818A1

    公开(公告)日：2021-04-22

    申请号：US17137262

    申请日：2020-12-29

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Aaron Cadag ,  Lester Joseph Belalo ,  Ela Mia Cadag

    IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

    Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame. This differential in height reduces the span of wires used to form electrical connections within the semiconductor package. These reductions in the span of the wires reduces the chances of wire to wire and wire to die short circuiting because the wire sweep of the wires is reduced when the molding compound is placed.

    Package with backside protective layer during molding to prevent mold flashing failure
    18.
    发明授权
    Package with backside protective layer during molding to prevent mold flashing failure 有权

    公开(公告)号：US10461019B2

    公开(公告)日：2019-10-29

    申请号：US16136709

    申请日：2018-09-20

    Applicant: STMicroelectronics, Inc.

    Inventor： Aaron Cadag ,  Ian Harvey Arellano ,  Ela Mia Cadag

    IPC: H01L21/44 ,  H01L23/495 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L23/544

    Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.

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