公开(公告)号：US20140176216A1

公开(公告)日：2014-06-26

申请号：US14134167

申请日：2013-12-19

Applicant: Commissariat à I'énergie atomique et aux énergies alternatives ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Yvain Thonnart ,  Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel

IPC: H03K3/012 ,  H01L27/12 ,  G05F3/02

CPC classification number: H03K3/012 ,  G05F3/02 ,  G06F1/10 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/78648

Abstract: The invention relates to an integrated circuit comprising: a block comprising: first (38) and second (40) oppositely doped semiconductor wells; standard cells (42, 43) placed next to one another, each standard cell (42) comprising first transistors (60, 62), and a clock tree cell (30) encircled by standard cells, the clock tree cell (30) comprising: a third semiconductor well (104) having the same doping type as the doping of the first well (38); second transistors (100, 102); a semiconductor strip (106) extending continuously around the third well (104), and having the opposite doping type to the doping of the third well, so as to electrically isolate the third well (104) from the first well (38).

Abstract translation: 本发明涉及一种集成电路，包括：块，包括：第一（38）和第二（40）相对掺杂的半导体阱; 时钟树单元（30）包括：标准单元（42,43），其彼此相邻放置，每个标准单元（42）包括第一晶体管（60,62）和由标准单元包围的时钟树单元（30） 具有与所述第一阱（38）的掺杂相同的掺杂类型的第三半导体阱（104）; 第二晶体管（100,102）; 围绕第三阱（104）连续延伸的半导体条（106），并且具有与第三阱的掺杂相反的掺杂类型，从而将第三阱（104）与第一阱（38）电隔离。

公开(公告)号：US20130121070A1

公开(公告)日：2013-05-16

申请号：US13669226

申请日：2012-11-05

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Maximilien Glorieux ,  Sylvain Clerc ,  Gilles Gasiot ,  Phillippe Roche

IPC: G11C11/40

CPC classification number: G11C19/28

Abstract: A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A first control circuit is configured to control a gate node of the first transistor based on the voltage at the second node and at a gate node of the second transistor. A second control circuit is configured to control the gate node of the second transistor based on the voltage at the first node and at the gate node of the first transistor.

Abstract translation: 存储器装置包括交叉耦合在第一和第二节点之间的第一和第二反相器。 第一反相器被配置为经由第一晶体管由第一电源电压提供，并且第二反相器被配置为经由第二晶体管由第一电源电压提供。 第一控制电路被配置为基于第二节点处的电压和第二晶体管的栅极节点来控制第一晶体管的栅极节点。 第二控制电路被配置为基于第一晶体管的第一节点处和栅极节点处的电压来控制第二晶体管的栅极节点。

公开(公告)号：US10684326B2

公开(公告)日：2020-06-16

申请号：US16031395

申请日：2018-07-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sylvain Clerc ,  Gilles Gasiot

IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/3183 ,  G01R31/317

Abstract: A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.

公开(公告)号：US10451670B2

公开(公告)日：2019-10-22

申请号：US15378663

申请日：2016-12-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sylvain Clerc

IPC: G01R31/28 ,  G01R31/30 ,  G01R31/317 ,  H03K5/133 ,  H03K19/003

Abstract: A device for monitoring a critical path of an integrated circuit includes a replica of the critical path formed by sequential elements mutually separated by delay circuits that are programmable though a corresponding main multiplexer. A control circuit controls delay selections made by each main multiplexer. A sequencing module operates to sequence each sequential element using a main clock signal by delivering, in response to a main clock signal, respectively to the sequential elements, secondary clock signals that are mutually time shifted in such a manner as to take into account the propagation time inherent to the main multiplexer.

公开(公告)号：US20170299651A1

公开(公告)日：2017-10-19

申请号：US15378663

申请日：2016-12-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sylvain Clerc

IPC: G01R31/28

CPC classification number: G01R31/2882 ,  G01R31/3016 ,  G01R31/31725 ,  H03K5/133 ,  H03K19/00369

Abstract: A device for monitoring a critical path of an integrated circuit includes a replica of the critical path formed by sequential elements mutually separated by delay circuits that are programmable though a corresponding main multiplexer. A control circuit controls delay selections made by each main multiplexer. A sequencing module operates to sequence each sequential element using a main clock signal by delivering, in response to a main clock signal, respectively to the sequential elements, secondary clock signals that are mutually time shifted in such a manner as to take into account the propagation time inherent to the main multiplexer.

公开(公告)号：US20140292374A1

公开(公告)日：2014-10-02

申请号：US14225520

申请日：2014-03-26

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Philippe Roche ,  Yvain Thonnart

IPC: H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/0016 ,  H01L27/0928 ,  H01L27/11807 ,  H01L27/1203 ,  H03K19/0013 ,  H03K19/01855 ,  H03K2217/0018

Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

Abstract translation: 一种用于控制具有逻辑单元和时钟树单元的IC的方法。 每个逻辑单元分别具有第一和第二FET，分别是pMOS和nMOS。 时钟树单元包括分别为pMOS和nMOS的第三和第四FET。 时钟树单元为逻辑单元提供时钟信号。 pMOS-FET的背栅电位差（“BGPD”）是其源电位减去其背栅电位之间的差异，反之亦然是nMOS-FET。 该方法包括将第一和第二后门电位差（BGPD）应用于逻辑单元的第一和第二FET，以及将第三BGPD应用于第三FET，其中第三BGPD为正并且大于施加的第一BGPD，其被应用 同时或将第四BGEPD应用于第四FET，其中第四BGPD为正并且大于并发应用的第二BGPD。

公开(公告)号：US10048317B2

公开(公告)日：2018-08-14

申请号：US15244586

申请日：2016-08-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sylvain Clerc ,  Gilles Gasiot

IPC: G01R31/3177 ,  G01R31/317

Abstract: A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.

公开(公告)号：US09479168B2

公开(公告)日：2016-10-25

申请号：US14225520

申请日：2014-03-26

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Philippe Roche ,  Yvain Thonnart

IPC: H03K19/096 ,  H03K19/00 ,  H01L27/092 ,  H01L27/118 ,  H01L27/12 ,  H03K19/0185

CPC classification number: H03K19/0016 ,  H01L27/0928 ,  H01L27/11807 ,  H01L27/1203 ,  H03K19/0013 ,  H03K19/01855 ,  H03K2217/0018

Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

Abstract translation: 一种用于控制具有逻辑单元和时钟树单元的IC的方法。 每个逻辑单元分别具有第一和第二FET，分别是pMOS和nMOS。 时钟树单元包括分别为pMOS和nMOS的第三和第四FET。 时钟树单元为逻辑单元提供时钟信号。 pMOS-FET的背栅电位差（“BGPD”）是其源电位减去其背栅电位之间的差异，反之亦然是nMOS-FET。 该方法包括将第一和第二后门电位差（BGPD）应用于逻辑单元的第一和第二FET，以及将第三BGPD应用于第三FET，其中第三BGPD为正并且大于施加的第一BGPD，其被应用 同时或将第四BGEPD应用于第四FET，其中第四BGPD为正并且大于并发应用的第二BGPD。

公开(公告)号：US09417282B2

公开(公告)日：2016-08-16

申请号：US14662530

申请日：2015-03-19

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Marc Daveau ,  Sylvain Clerc ,  Philippe Roche

IPC: G06F11/08 ,  G01R31/3177 ,  G06F11/267 ,  G01R31/3185 ,  G06F11/18

CPC classification number: G01R31/3177 ,  G01R31/318502 ,  G06F11/183 ,  G06F11/267

Abstract: A method for managing operation of a logic component is provided, with the logic component including a majority vote circuit and an odd number of flip-flops equal to at least three. The method includes, following a normal operating mode of the logic component, placing a flip-flop in a test mode, and injecting a test signal into a test input of the flip-flop being tested while a logic state of the other flip-flops is frozen. A test signal output is analyzed. At the end of the test, the logic component is placed back in the normal operating mode. The majority vote circuit restores a value of the output signal from the logic component that existed prior to initiation of the test.

Abstract translation: 提供了一种用于管理逻辑部件的操作的方法，其中逻辑部件包括等于至少三个的多数投票电路和奇数触发器。 该方法包括：遵循逻辑部件的正常操作模式，将触发器置于测试模式，并将测试信号注入被测试的触发器的测试输入，而其它触发器的逻辑状态 被冻结。 分析测试信号输出。 在测试结束时，将逻辑组件放回正常操作模式。 多数投票电路恢复来自在开始测试之前存在的逻辑组件的输出信号的值。