-
公开(公告)号：US10049991B2
公开(公告)日：2018-08-14
申请号：US15596772
申请日：2017-05-16
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Christian Rivero , Pascal Fornara , Guilhem Bouton , Mathieu Lisart
IPC: H01L23/522 , H01L21/70 , H01L21/768 , H01L23/52 , H01L23/00 , H01L23/28 , H01L23/528 , H01L21/56
Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer. An electrical discontinuity between a first via of the via level and a first metal track of the lower metallization level is provided at the level of the insulating encapsulation layer. The electrical discontinuity is formed prior to formation of any via of the via level and prior to any metal track of the upper metallization level. The electrical discontinuity may comprise: a portion of an additional insulating layer extending over the insulating encapsulation layer; a portion of the insulating encapsulation layer; or an insulating oxide on a top surface of the first metal track.
-
公开(公告)号：US10049982B2
公开(公告)日：2018-08-14
申请号：US15596877
申请日：2017-05-16
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Christian Rivero , Pascal Fornara , Guilhem Bouton , Mathieu Lisart
IPC: H01L21/768 , H01L23/522 , H01L23/528
Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer and an inter-metallization level insulating layer. An electrical discontinuity is provided between a via of the via level and a metal track of the lower metallization level. The electrical discontinuity is formed by an additional insulating layer having a material composition identical to that of the inter-metallization level insulating layer. The electrical discontinuity is situated between a bottom of the via and a top of the metal track, with the discontinuity being bordered by the insulating encapsulation layer.
-
13.发明申请公开(公告)号：US20180131508A1
公开(公告)日：2018-05-10
申请号：US15862962
申请日：2018-01-05
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Fabrice Marinet , Mathieu Lisart
CPC classification number: H04L9/088 , G06F3/0623 , G06F3/0644 , G06F3/0688 , G06F11/1458 , G06F12/1408 , G06F21/62 , G06F21/77 , G06F21/78 , G06F2212/402
Abstract: A method for processing content stored on a component is disclosed. A first partition of a first memory is encrypted with a first encryption key and a second partition of the first memory is encrypted with a second encryption key. The second encryption key is different from the first encryption key. The first encryption key is stored in a storage register of the component and the second encryption key is stored in a first location of a non-volatile memory. A memory address of the first location is stored in the first partition of the first memory.
-
14.发明授权公开(公告)号：US09900151B2
公开(公告)日：2018-02-20
申请号：US15056844
申请日：2016-02-29
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Fabrice Marinet , Mathieu Lisart
CPC classification number: H04L9/088 , G06F3/0623 , G06F3/0644 , G06F3/0688 , G06F11/1458 , G06F12/1408 , G06F21/62 , G06F21/77 , G06F21/78 , G06F2212/402
Abstract: A method for processing content stored on a component is disclosed. A first partition of a first memory is encrypted with a first encryption key and a second partition of the first memory is encrypted with a second encryption key. The second encryption key is different from the first encryption key. The first encryption key is stored in a storage register of the component and the second encryption key is stored in a first location of a non-volatile memory. A memory address of the first location is stored in the first partition of the first memory.
-
公开(公告)号：US09052345B2
公开(公告)日：2015-06-09
申请号：US13654991
申请日：2012-10-18
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Mathieu Lisart , Thierry Soude
CPC classification number: G01R27/08 , G01R31/2856 , G01R31/311 , G01R31/31719 , G09C1/00 , H01L23/576 , H01L2924/0002 , H04L9/004 , H04L2209/12 , H01L2924/00
Abstract: A system for detecting a laser attack on an integrated circuit chip formed in a semiconductor substrate, including a detection device capable of detecting voltage variations of the substrate. The system includes P-type first wells and N-type second wells extending in a P-type upper portion of the substrate; an N-type buried layer extending under at least a portion of the first and second wells; biasing contacts for the second wells and the buried layer; ground contacts for the first wells; and substrate contacts for detecting a substrate voltage, the detection contacts surrounding the first and second wells. The detection device comprises a resistor having a first terminal connected to said ground contacts of the first wells and a second terminal connected to said substrate contacts; and a comparator connected in with the resistor configured to detect a potential difference across the resistor.
Abstract translation: 一种用于检测形成在半导体衬底中的集成电路芯片上的激光攻击的系统，包括能够检测衬底的电压变化的检测装置。 该系统包括在基板的P型上部中延伸的P型第一阱和N型第二阱; 在所述第一和第二孔的至少一部分下延伸的N型掩埋层; 用于第二井和埋层的偏压接触; 第一口井的地面接触; 以及用于检测衬底电压的衬底触点，围绕第一和第二阱的检测触点。 检测装置包括电阻器，其具有连接到第一阱的所述接地触点的第一端子和连接到所述衬底触点的第二端子; 以及与电阻器连接的比较器，被配置为检测电阻器两端的电位差。
-
Patent Agency Ranking
公开(公告)号：US11640844B2
公开(公告)日：2023-05-02
申请号：US17010400
申请日：2020-09-02
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Fabrice Romain , Mathieu Lisart
Abstract: A method for detecting a writing error of a datum in memory includes: storing at least two parts of equal size of a binary word representative of said datum at the same address in at least two identical memory circuits, and comparing internal control signals of the two memory circuits to determine existence of the writing error.
-
公开(公告)号：US11374569B2
公开(公告)日：2022-06-28
申请号：US17413459
申请日：2019-11-28
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Nicolas Borrel , Jimmy Fort , Mathieu Lisart
IPC: H03K5/22 , H03K19/003 , H03K19/00 , H03K19/17736 , H03F3/45 , H03L7/097 , H04L9/32
Abstract: The physically unclonable function device (DIS) comprises a set of MOS transistors (TR1i, TR2j) mounted in diodes having a random distribution of respective threshold voltages, and comprising N first transistors and at least one second transistor. At least one output node of the function is capable of delivering a signal, the level of which depends on the comparison between a current obtained using a current circulating in the at least one second transistor and a current obtained using a reference current that is equal or substantially equal to the average of the currents circulating in the N first transistors. A first means (FM1i) is configured to impose on each first transistor a respective fixed gate voltage regardless of the value of the current circulating in the first transistor, and a second means (SM2j) is configured to impose a respective fixed gate voltage on each second transistor regardless of the value of the current circulating in the second transistor.
-
公开(公告)号：US10833027B2
公开(公告)日：2020-11-10
申请号：US15784883
申请日：2017-10-16
Inventor： Mathieu Lisart , Raul Andres Bianchi , Benoit Froment
IPC: G01L23/00 , H01L23/00 , H04L9/32 , H04L9/00 , G06F9/4401 , H01L21/265 , H01L21/266 , H01L21/3205 , H01L21/8234 , H01L23/528 , H01L27/088 , H03K17/14
Abstract: An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.
-
19.发明授权公开(公告)号：US10389530B2
公开(公告)日：2019-08-20
申请号：US15862962
申请日：2018-01-05
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Fabrice Marinet , Mathieu Lisart
Abstract: A method for processing content stored on a component is disclosed. A first partition of a first memory is encrypted with a first encryption key and a second partition of the first memory is encrypted with a second encryption key. The second encryption key is different from the first encryption key. The first encryption key is stored in a storage register of the component and the second encryption key is stored in a first location of a non-volatile memory. A memory address of the first location is stored in the first partition of the first memory.
-
公开(公告)号：US10389521B2
公开(公告)日：2019-08-20
申请号：US15138573
申请日：2016-04-26
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Mathieu Lisart , Benoit Durand , Massimo Cervetto , Christophe Laurencin
Abstract: A circuit includes a first processing unit and a second identical processing unit. A first communication bus passes encrypted data between one of a plurality of functions and one or both of the first and second processing units. A selection circuit determines whether the encrypted bus is coupled to the first processing unit, the second processing unit, or both of the first and second processing units.
-
-
-
-
-
-
-
-
-
Search Results
53
records
(took 0.021 seconds)
