公开(公告)号：US20220028978A1

公开(公告)日：2022-01-27

申请号：US17374871

申请日：2021-07-13

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Simone RASCUNÁ ,  Mario Giuseppe SAGGIO

IPC: H01L29/16 ,  H01L29/872 ,  H01L29/66

Abstract: Merged-PiN-Schottky, MPS, device comprising: a substrate of SiC with a first conductivity; a drift layer of SiC with the first conductivity, on the substrate; an implanted region with a second conductivity, extending at a top surface of the drift layer to form a junction-barrier, JB, diode with the substrate; and a first electrical terminal in ohmic contact with the implanted region and in direct contact with the top surface to form a Schottky diode with the drift layer. The JB diode and the Schottky diode are alternated to each other along an axis: the JB diode has a minimum width parallel to the axis with a first value, and the Schottky diode has a maximum width parallel to the axis with a second value smaller than, or equal to, the first value. A breakdown voltage of the MPS device is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.

公开(公告)号：US20210151563A1

公开(公告)日：2021-05-20

申请号：US17096635

申请日：2020-11-12

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe SAGGIO ,  Edoardo ZANETTI ,  Alfio GUARNERA

IPC: H01L29/08 ,  H01L29/16

Abstract: A MOSFET device includes a semiconductor body having a first and a second face. A source terminal of the MOSFET device includes a doped region which extends at the first face of the semiconductor body and a metal layer electrically coupled to the doped region. A drain terminal extends at the second face of the semiconductor body. The doped region includes a first sub-region having a first doping level and a first depth, and a second sub-region having a second doping level and a second depth. At least one among the second doping level and the second maximum depth has a value which is higher than a respective value of the first doping level and the first maximum depth. The metal layer is in electrical contact with the source terminal exclusively through the second sub-region.

公开(公告)号：US20200235248A1

公开(公告)日：2020-07-23

申请号：US16841536

申请日：2020-04-06

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Mario Giuseppe SAGGIO ,  Simone RASCUNA'

IPC: H01L29/872 ,  H01L29/66 ,  H01L23/535 ,  H01L21/768 ,  H01L21/225 ,  H01L29/16 ,  H01L29/06 ,  H01L29/417

Abstract: A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.

公开(公告)号：US20190013312A1

公开(公告)日：2019-01-10

申请号：US16027060

申请日：2018-07-03

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Mario Giuseppe SAGGIO ,  Simone RASCUNÁ

IPC: H01L27/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/872 ,  H01L21/04

Abstract: An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode.

公开(公告)号：US20240178280A1

公开(公告)日：2024-05-30

申请号：US18532975

申请日：2023-12-07

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Simone RASCUNA' ,  Mario Giuseppe SAGGIO

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/872

CPC classification number: H01L29/1608 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/872

Abstract: Merged-PiN-Schottky, MPS, device comprising: a substrate of SiC with a first conductivity; a drift layer of SiC with the first conductivity, on the substrate; an implanted region with a second conductivity, extending at a top surface of the drift layer to form a junction-barrier, JB, diode with the substrate; and a first electrical terminal in ohmic contact with the implanted region and in direct contact with the top surface to form a Schottky diode with the drift layer. The JB diode and the Schottky diode are alternated to each other along an axis: the JB diode has a minimum width parallel to the axis with a first value, and the Schottky diode has a maximum width parallel to the axis with a second value smaller than, or equal to, the first value. A breakdown voltage of the MPS device is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.

公开(公告)号：US20240079455A1

公开(公告)日：2024-03-07

申请号：US18364180

申请日：2023-08-02

Applicant: STMicroelectronics S.r.l.

Inventor： Patrick FIORENZA ,  Fabrizio ROCCAFORTE ,  Edoardo ZANETTI ,  Mario Giuseppe SAGGIO

IPC: H01L29/16 ,  H01L29/51 ,  H01L29/66 ,  H01L29/872

CPC classification number: H01L29/1608 ,  H01L29/511 ,  H01L29/66068 ,  H01L29/872

Abstract: Electronic device comprising: a semiconductor body, in particular of Silicon Carbide, SiC, having a first and a second face, opposite to each other along a first direction; and an electrical terminal at the first face, insulated from the semiconductor body by an electrical insulation region. The electrical insulation region is a multilayer comprising: a first insulating layer, of a Silicon Oxide, in contact with the semiconductor body; a second insulating layer on the first insulating layer, of a Hafnium Oxide; and a third insulating layer on the second insulating layer, of an Aluminum Oxide.

公开(公告)号：US20230099610A1

公开(公告)日：2023-03-30

申请号：US18061795

申请日：2022-12-05

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Edoardo ZANETTI ,  Simone RASCUNA' ,  Mario Giuseppe SAGGIO ,  Alfio GUARNERA ,  Leonardo FRAGAPANE ,  Cristina TRINGALI

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/872 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US20220246771A1

公开(公告)日：2022-08-04

申请号：US17592322

申请日：2022-02-03

Applicant: STMicroelectronics S.r.l.

Inventor： Simone RASCUNA' ,  Gabriele BELLOCCHI ,  Edoardo ZANETTI ,  Mario Giuseppe SAGGIO

IPC: H01L29/872 ,  H01L29/16 ,  H01L29/66

Abstract: A vertical conduction electronic device is formed by a body of wide-bandgap semiconductor material having a first conductivity type and a surface, which defines a first direction and a second direction. The body has a drift region. The electronic device includes a plurality of superficial implanted regions having a second conductivity type, which extend in the drift region from the surface and delimit between them, in the drift region, at least one superficial portion facing the surface. At least one deep implanted region has the second conductivity type, and extends in the drift region, at a distance from the surface of the body. A metal region extends on the surface of the body, in Schottky contact with the superficial portion of the drift region.

公开(公告)号：US20220157989A1

公开(公告)日：2022-05-19

申请号：US17665398

申请日：2022-02-04

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe SAGGIO ,  Edoardo ZANETTI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/16 ,  H01L29/06 ,  H01L29/10

Abstract: A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.

公开(公告)号：US20220076955A1

公开(公告)日：2022-03-10

申请号：US17458102

申请日：2021-08-26

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Simone RASCUNA' ,  Mario Giuseppe SAGGIO

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/66

Abstract: A manufacturing method of an anchorage element of a passivation layer, comprising: forming, in a semiconductor body made of SiC and at a distance from a top surface of the semiconductor body, a first implanted region having, along a first axis, a first maximum dimension; forming, in the semiconductor body, a second implanted region, which is superimposed to the first implanted region and has, along the first axis, a second maximum dimension smaller than the first maximum dimension; carrying out a process of thermal oxidation of the first implanted region and second implanted region to form an oxidized region; removing said oxidized region to form a cavity; and forming, on the top surface, the passivation layer protruding into the cavity to form said anchorage element fixing the passivation layer to the semiconductor body.