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公开(公告)号：US20220317184A1
公开(公告)日：2022-10-06
申请号：US17709053
申请日：2022-03-30
Inventor： Franck Albesa , Nicolas Anquet
IPC: G01R31/317 , G06F21/60 , G06F21/75
Abstract: In an embodiment a method for debugging a processing device includes generating, by a monotonic counter of the processing device, a first count value, transmitting, by the monotonic counter, the first count value to a debug access control circuit, comparing, by the debug access control circuit of the processing device, the first count value with one or more reference values and authorizing or preventing debug access, by the debug access control circuit, based on the comparison.
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公开(公告)号：US11914718B2
公开(公告)日：2024-02-27
申请号：US17657027
申请日：2022-03-29
Inventor： Franck Albesa , Nicolas Anquet
IPC: G06F21/57 , G06F9/4401 , G06F21/60
CPC classification number: G06F21/575 , G06F9/4403 , G06F21/602 , G06F2221/034
Abstract: The present disclosure relates to a method for booting a processing device, the method including: generating, by a monotonic counter and during a first boot phase, a first count value; transmitting, by the monotonic counter, the first count value to an access control circuit of a memory; reading, on the basis of the first count value, first data stored in the memory; and generating, by the monotonic counter and during a second boot phase, a second count value greater than the first count value. The access control circuit of the memory is configured so that the reading of the first data is not authorized on the basis of the second count value.
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13.发明公开公开(公告)号：US20230291645A1
公开(公告)日：2023-09-14
申请号：US18321516
申请日：2023-05-22
Inventor： Nicolas Anquet , Loic Pallardy
IPC: H04L41/0813 , H04L49/109 , G06F15/173 , G06F15/177 , H04L41/0803
CPC classification number: H04L41/0813 , H04L49/109 , G06F15/17306 , G06F15/177 , H04L41/0803 , G06F21/85
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
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公开(公告)号：US20230161485A1
公开(公告)日：2023-05-25
申请号：US17993618
申请日：2022-11-23
Inventor： Loic Pallardy , Nicolas Anquet
IPC: G06F3/06
CPC classification number: G06F3/0622 , G06F3/0637 , G06F3/0673
Abstract: In accordance with an embodiment, a system on chip includes: a plurality of master equipment; a plurality of slave resources, where a slave resource of the plurality of slave resources comprises a memory device includes a first memory area; an interconnection circuit; and a check circuit. A first master equipment is configured to define initial access rights for the first memory area, and to delegate access management of the first memory area to a second master equipment. The second master equipment is configured to define for the first memory area, particular access rights from the initial access rights associated with the first memory area and access right rules; and the check circuit is configured to check whether a transaction intended for the first memory area is indeed authorized to access the first memory area using applicable access rights associated with the first memory area.
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公开(公告)号：US20210160134A1
公开(公告)日：2021-05-27
申请号：US16951198
申请日：2020-11-18
Inventor： Nicolas Anquet , Loic Pallardy
IPC: H04L12/24 , H04L12/933
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
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Patent Agency Ranking
公开(公告)号：US11876732B2
公开(公告)日：2024-01-16
申请号：US17100505
申请日：2020-11-20
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS , STMicroelectronics (Grand Ouest) SAS
Inventor： Daniel Olson , Loic Pallardy , Nicolas Anquet
IPC: H04L41/0803 , H04L49/109 , G06F21/85
CPC classification number: H04L49/109 , G06F21/85 , H04L41/0803
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.
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公开(公告)号：US11700174B2
公开(公告)日：2023-07-11
申请号：US16951198
申请日：2020-11-18
Inventor： Nicolas Anquet , Loic Pallardy
IPC: H04L41/0803 , H04L41/0813 , H04L49/109 , G06F15/173 , G06F15/177 , G06F21/85
CPC classification number: H04L41/0813 , G06F15/177 , G06F15/17306 , H04L41/0803 , H04L49/109 , G06F21/85
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
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18.发明授权公开(公告)号：US11698993B2
公开(公告)日：2023-07-11
申请号：US17161544
申请日：2021-01-28
Inventor： Gilles Pelissier , Nicolas Anquet , Delphine Le-Goascoz
CPC classification number: G06F21/72 , H04L9/06 , H04L9/0866 , G06F2221/2113
Abstract: A unique hardware key is recorded a secure hardware environment. A first logic circuit of the secure hardware environment is configured to generate a unique derived key from said unique hardware key and at least one piece of information. The at least one piece of information relates to one or more of an execution context and a use of a secret key. The secure hardware environment further includes a first encryption device that performs a symmetric encryption of the secret key using the unique derived key. This symmetric encryption generates an encrypted secret key for use outside of the secure hardware environment.
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19.发明授权公开(公告)号：US11610025B2
公开(公告)日：2023-03-21
申请号：US17161194
申请日：2021-01-28
Inventor： Gilles Pelissier , Nicolas Anquet , Delphine Le-Goascoz
Abstract: An integrated circuit includes a secure hardware environment having a first input that receives a key number. A key generation device generates a secret key from the key number and a unique key. A signature generation device generates a signature associated with the key number. A second input of the secure hardware environment receives encrypted binary data. A decryption device operates to decrypt the received encrypted binary data using the secret key. A third input the secure hardware environment receives an authentication signature. An authentication device authorizes use of the secret key to decrypt only if the signature generated by the signature generation device is identical to the authentication signature.
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公开(公告)号：US20220318392A1
公开(公告)日：2022-10-06
申请号：US17657027
申请日：2022-03-29
Inventor： Franck Albesa , Nicolas Anquet
IPC: G06F21/57 , G06F21/60 , G06F9/4401
Abstract: The present disclosure relates to a method for booting a processing device, the method including: generating, by a monotonic counter and during a first boot phase, a first count value; transmitting, by the monotonic counter, the first count value to an access control circuit of a memory; reading, on the basis of the first count value, first data stored in the memory; and generating, by the monotonic counter and during a second boot phase, a second count value greater than the first count value. The access control circuit of the memory is configured so that the reading of the first data is not authorized on the basis of the second count value.
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