公开(公告)号：US10948611B2

公开(公告)日：2021-03-16

申请号：US15981321

申请日：2018-05-16

申请人： STMicroelectronics (Crolles 2) SAS ,  Centre National De La Recherche Scientifique ,  UNIVERSITE D'AIX MARSEILLE ,  UNIVERSITE DE TOULON

发明人： Martin Cochet ,  Dimitri Soussan ,  Fady Abouzeid ,  Gilles Gasiot ,  Philippe Roche

IPC分类号： G01T1/02 ,  H03K3/03

摘要： Absorbed ionizing particles differentially effect first and second acquiring circuit stages configured to respectively generate first and second acquisition signals. Each acquisition signal has a characteristic that is variable as a function of an amount of absorbed ionizing particles. A measuring circuit generates, on the basis of the first and second acquisition signals, a relative parameter indicative of a relationship between the variable characteristics. A computation of a total ionizing dose is made using a 1st- or 2nd-degree polynomial relationship in the relative parameter.

公开(公告)号：US09748955B1

公开(公告)日：2017-08-29

申请号：US15363041

申请日：2016-11-29

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Gilles Gasiot ,  Victor Malherbe ,  Sylvain Clerc

IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K19/21 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H03K19/00338 ,  H01L21/823892 ,  H01L27/0266 ,  H01L27/092 ,  H01L27/0928 ,  H03K19/21

摘要： A radiation-hardened logic device includes a first n-channel transistor coupled by its main conducting nodes between an output node of a logic device and a supply voltage rail and a first p-channel transistor coupled by its main conducting nodes between the output node of the logic device and a ground voltage rail. The gates of the first n-channel and p-channel transistors are coupled to the output node.

公开(公告)号：US08837206B2

公开(公告)日：2014-09-16

申请号：US13669226

申请日：2012-11-05

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Maximilien Glorieux ,  Sylvain Clerc ,  Gilles Gasiot ,  Phillippe Roche

IPC分类号： G11C11/00

CPC分类号： G11C19/28

摘要： A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A first control circuit is configured to control a gate node of the first transistor based on the voltage at the second node and at a gate node of the second transistor. A second control circuit is configured to control the gate node of the second transistor based on the voltage at the first node and at the gate node of the first transistor.

摘要翻译： 存储器装置包括交叉耦合在第一和第二节点之间的第一和第二反相器。 第一反相器被配置为经由第一晶体管由第一电源电压提供，并且第二反相器被配置为经由第二晶体管由第一电源电压提供。 第一控制电路被配置为基于第二节点处的电压和第二晶体管的栅极节点来控制第一晶体管的栅极节点。 第二控制电路被配置为基于第一晶体管的第一节点处和栅极节点处的电压来控制第二晶体管的栅极节点。

公开(公告)号：US20130121070A1

公开(公告)日：2013-05-16

申请号：US13669226

申请日：2012-11-05

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Maximilien Glorieux ,  Sylvain Clerc ,  Gilles Gasiot ,  Phillippe Roche

IPC分类号： G11C11/40

CPC分类号： G11C19/28

摘要： A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A first control circuit is configured to control a gate node of the first transistor based on the voltage at the second node and at a gate node of the second transistor. A second control circuit is configured to control the gate node of the second transistor based on the voltage at the first node and at the gate node of the first transistor.

摘要翻译： 存储器装置包括交叉耦合在第一和第二节点之间的第一和第二反相器。 第一反相器被配置为经由第一晶体管由第一电源电压提供，并且第二反相器被配置为经由第二晶体管由第一电源电压提供。 第一控制电路被配置为基于第二节点处的电压和第二晶体管的栅极节点来控制第一晶体管的栅极节点。 第二控制电路被配置为基于第一晶体管的第一节点处和栅极节点处的电压来控制第二晶体管的栅极节点。