公开(公告)号：US11653582B2

公开(公告)日：2023-05-16

申请号：US16184246

申请日：2018-11-08

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H10N70/8616 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/8413 ,  H10N70/882 ,  G11C2013/008

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

公开(公告)号：US20180158861A1

公开(公告)日：2018-06-07

申请号：US15866995

申请日：2018-01-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Lagrasta ,  Delia Ristoiu ,  Jean-Pierre Oddou ,  Cécile Jenny

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14654 ,  H01L27/14685 ,  H01L27/14689

Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.

公开(公告)号：US09917126B1

公开(公告)日：2018-03-13

申请号：US15263922

申请日：2016-09-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Lagrasta ,  Delia Ristoiu ,  Jean-Pierre Oddou ,  Cécile Jenny

IPC: H01L31/062 ,  H01L31/113 ,  H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14654 ,  H01L27/14685 ,  H01L27/14689

Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.

公开(公告)号：US20160099278A1

公开(公告)日：2016-04-07

申请号：US14847391

申请日：2015-09-08

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Guyader ,  Jean-Pierre Oddou ,  Stephane Allegret-Maret ,  Mickael Gros-Jean

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/1203 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/1464

Abstract: A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels. A continuous electrically conductive layer forms, in the zone of pixels, an electrode in a trench for each capacitive deep trench isolation, and forms, in the peripheral zone, a redistribution layer for electrically coupling the electrode to a biasing contact pad. The electrode is located in the trench between a trench dielectric and at least one material for filling the trench.

Abstract translation: 背照式集成成像装置由包括由电容深沟槽隔离限制的像素区域的半导体衬底形成。 外围区域位于像素区域之外。 连续导电层在像素区域中形成用于每个电容深沟槽隔离的沟槽中的电极，并且在周边区域中形成用于将电极电耦合到偏置接触焊盘的再分布层。 电极位于沟槽电介质和用于填充沟槽的至少一种材料之间的沟槽中。

公开(公告)号：US20140004644A1

公开(公告)日：2014-01-02

申请号：US13858481

申请日：2013-04-08

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles 2) SAS

Inventor： François Roy ,  Lucile Broussous ,  Julien Michelot ,  Jean-Pierre Oddou

IPC: H01L31/18

CPC classification number: H01L31/18 ,  H01L27/14605

Abstract: A method for manufacturing an image sensor, including the successive steps of: forming columns of a semiconductor material; forming one or several pixels at a first end of each of the columns; and deforming the structure so that the second ends of each of the columns come closer to each other or draw away from each other to form a surface in the shape of a polyhedral cap.

Abstract translation: 一种用于制造图像传感器的方法，包括以下连续步骤：形成半导体材料的列; 在每个列的第一端形成一个或几个像素; 并且使结构变形，使得每个柱的第二端彼此靠近或彼此拉开，以形成多面体盖的形状的表面。