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公开(公告)号：US09099604B2
公开(公告)日：2015-08-04
申请号：US13858481
申请日：2013-04-08
Inventor： François Roy , Lucile Broussous , Julien Michelot , Jean-Pierre Oddou
IPC: H01L21/00 , H01L31/18 , H01L27/146
CPC classification number: H01L31/18 , H01L27/14605
Abstract: A method for manufacturing an image sensor, including the successive steps of: forming columns of a semiconductor material; forming one or several pixels at a first end of each of the columns; and deforming the structure so that the second ends of each of the columns come closer to each other or draw away from each other to form a surface in the shape of a polyhedral cap.
Abstract translation: 一种用于制造图像传感器的方法，包括以下连续步骤：形成半导体材料的列; 在每个列的第一端形成一个或几个像素; 并且使结构变形使得每个柱的第二端彼此靠近或彼此拉开以形成多面体盖的形状的表面。
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公开(公告)号：US20140004644A1
公开(公告)日：2014-01-02
申请号：US13858481
申请日：2013-04-08
Inventor： François Roy , Lucile Broussous , Julien Michelot , Jean-Pierre Oddou
IPC: H01L31/18
CPC classification number: H01L31/18 , H01L27/14605
Abstract: A method for manufacturing an image sensor, including the successive steps of: forming columns of a semiconductor material; forming one or several pixels at a first end of each of the columns; and deforming the structure so that the second ends of each of the columns come closer to each other or draw away from each other to form a surface in the shape of a polyhedral cap.
Abstract translation: 一种用于制造图像传感器的方法，包括以下连续步骤：形成半导体材料的列; 在每个列的第一端形成一个或几个像素; 并且使结构变形，使得每个柱的第二端彼此靠近或彼此拉开，以形成多面体盖的形状的表面。
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公开(公告)号：US12232435B2
公开(公告)日：2025-02-18
申请号：US18130184
申请日：2023-04-03
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Franck Arnaud , David Galpin , Stephane Zoll , Olivier Hinsinger , Laurent Favennec , Jean-Pierre Oddou , Lucile Broussous , Philippe Boivin , Olivier Weber , Philippe Brun , Pierre Morin
Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.
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公开(公告)号：US20180076250A1
公开(公告)日：2018-03-15
申请号：US15263922
申请日：2016-09-13
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Sebastien Lagrasta , Delia Ristoiu , Jean-Pierre Oddou , Cécile Jenny
IPC: H01L27/146
CPC classification number: H01L27/14636 , H01L27/14623 , H01L27/1463 , H01L27/14641 , H01L27/14654 , H01L27/14685 , H01L27/14689
Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.
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公开(公告)号：US09685475B2
公开(公告)日：2017-06-20
申请号：US14847391
申请日：2015-09-08
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Francois Guyader , Jean-Pierre Oddou , Stephane Allegret-Maret , Mickael Gros-Jean
IPC: H01L31/18 , H01L31/0232 , H01L27/146 , H01L27/12
CPC classification number: H01L27/14636 , H01L27/1203 , H01L27/1462 , H01L27/14623 , H01L27/14629 , H01L27/1463 , H01L27/1464
Abstract: A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels. A continuous electrically conductive layer forms, in the zone of pixels, an electrode in a trench for each capacitive deep trench isolation, and forms, in the peripheral zone, a redistribution layer for electrically coupling the electrode to a biasing contact pad. The electrode is located in the trench between a trench dielectric and at least one material for filling the trench.
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Patent Agency Ranking
公开(公告)号：US09224775B2
公开(公告)日：2015-12-29
申请号：US14446804
申请日：2014-07-30
Applicant: STMicroelectronics (Crolles 2) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
IPC: H01L27/14 , H01L27/146
CPC classification number: H01L27/14625 , H01L27/1462 , H01L27/1464 , H01L27/14645 , H01L27/14685
Abstract: An integrated circuit includes a back side illuminated image sensor formed by a substrate supporting at least one pixel, an interconnect part situated above a front side of the substrate and an anti-reflective layer situated above a back side of the substrate. The anti-reflective layer may be formed of a silicon nitride layer. An additional layer is situated above the anti-reflective layer. The additional layer is formed of one of amorphous silicon nitride or hydrogenated amorphous silicon nitride, in which the ratio of the number of silicon atoms per cubic centimeter to the number of nitrogen atoms per cubic centimeter is greater than 0.7.
Abstract translation: 集成电路包括由支撑至少一个像素的衬底形成的背面照明图像传感器，位于衬底前侧之上的互连部分和位于衬底背面上方的抗反射层。 抗反射层可以由氮化硅层形成。 附加层位于抗反射层上方。 附加层由非晶氮化硅或氢化非晶氮化硅之一形成，其中每立方厘米的硅原子数与每立方厘米的氮原子数之比大于0.7。
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公开(公告)号：US10128295B2
公开(公告)日：2018-11-13
申请号：US15866995
申请日：2018-01-10
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Sebastien Lagrasta , Delia Ristoiu , Jean-Pierre Oddou , Cécile Jenny
IPC: H01L27/146
Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.
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公开(公告)号：US20180102387A1
公开(公告)日：2018-04-12
申请号：US15839292
申请日：2017-12-12
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics SA
Inventor： Axel Crocherie , Jean-Pierre Oddou , Stéphane Allegret-Maret , Hugues Leininger
IPC: H01L27/146
CPC classification number: H01L27/14621 , H01L27/14607 , H01L27/1463 , H01L27/14636 , H01L27/1464 , H01L27/14685
Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.
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公开(公告)号：US20150035106A1
公开(公告)日：2015-02-05
申请号：US14446804
申请日：2014-07-30
Applicant: STMicroelectronics (Crolles 2) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
IPC: H01L27/146
CPC classification number: H01L27/14625 , H01L27/1462 , H01L27/1464 , H01L27/14645 , H01L27/14685
Abstract: An integrated circuit includes a back side illuminated image sensor formed by a substrate supporting at least one pixel, an interconnect part situated above a front side of the substrate and an anti-reflective layer situated above a back side of the substrate. The anti-reflective layer may be formed of a silicon nitride layer. An additional layer is situated above the anti-reflective layer. The additional layer is formed of one of amorphous silicon nitride or hydrogenated amorphous silicon nitride, in which the ratio of the number of silicon atoms per cubic centimeter to the number of nitrogen atoms per cubic centimeter is greater than 0.7.
Abstract translation: 集成电路包括由支撑至少一个像素的衬底形成的背面照明图像传感器，位于衬底前侧之上的互连部分和位于衬底背面上方的抗反射层。 抗反射层可以由氮化硅层形成。 附加层位于抗反射层上方。 附加层由非晶氮化硅或氢化非晶氮化硅之一形成，其中每立方厘米的硅原子数与每立方厘米的氮原子数之比大于0.7。
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公开(公告)号：US11653582B2
公开(公告)日：2023-05-16
申请号：US16184246
申请日：2018-11-08
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Franck Arnaud , David Galpin , Stephane Zoll , Olivier Hinsinger , Laurent Favennec , Jean-Pierre Oddou , Lucile Broussous , Philippe Boivin , Olivier Weber , Philippe Brun , Pierre Morin
CPC classification number: H10N70/8616 , G11C13/0004 , G11C13/0069 , H10B63/30 , H10B63/80 , H10N70/011 , H10N70/021 , H10N70/231 , H10N70/826 , H10N70/8265 , H10N70/8413 , H10N70/882 , G11C2013/008
Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.
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