公开(公告)号：US10141396B2

公开(公告)日：2018-11-27

申请号：US15444644

申请日：2017-02-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Clement Champeix ,  Nicolas Borrel ,  Alexandre Sarafianos

IPC: G06F21/78 ,  H01L29/06 ,  G06F21/88 ,  G06F21/77 ,  H01L27/06 ,  H01L29/10 ,  H03K5/24 ,  G06F21/75 ,  G06F21/87 ,  H01L23/00 ,  H01L29/66

Abstract: An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.

公开(公告)号：US10079215B2

公开(公告)日：2018-09-18

申请号：US15789362

申请日：2017-10-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Mathieu Lisart ,  Jimmy Fort

IPC: H01L23/00 ,  H01L21/762 ,  H01L27/088

CPC classification number: H01L23/576 ,  H01L21/762 ,  H01L27/088

Abstract: An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity type arranged alternately and contiguously on a region of the first conductivity type; two detection contacts arranged at the ends of each second bar; a circuit for detecting the resistance between the detection contacts of each second bar; insulating trenches extending in the second bars down to a first depth between circuit elements; and insulating walls extending across the entire width of each second bar down to a second depth greater than the first depth.

公开(公告)号：US20170250795A1

公开(公告)日：2017-08-31

申请号：US15221749

申请日：2016-07-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Thomas Ordas ,  Alexandre Sarafianos ,  Stephane Chesnais ,  Fabrice Marinet

IPC: H04L9/00 ,  G06F21/72 ,  H03K5/01 ,  H01L23/528 ,  G06F1/04 ,  H03K3/84

CPC classification number: H04L9/002 ,  G06F1/04 ,  G06F21/72 ,  G06K19/07336 ,  G09C1/00 ,  H01L23/528 ,  H03K3/84 ,  H03K5/01 ,  H03K2005/00019 ,  H04K3/825 ,  H04K2203/32 ,  H04L9/003 ,  H04L2209/08 ,  H04L2209/805

Abstract: A device is provided for jamming electromagnetic radiation liable to be emitted by at least one portion of an interconnect region located above at least one zone of an integrated electronic circuit produced in and on a semiconductor substrate. The device includes an antenna located above the at least one zone of the circuit and generating circuit coupled to the antenna and configured to generate an electrical signal having at least one pseudo-random property to pass through the antenna.

公开(公告)号：US11562933B2

公开(公告)日：2023-01-24

申请号：US16800448

申请日：2020-02-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Abderrezak Marzaki

IPC: H01L21/66 ,  H01L23/00 ,  H03K19/00 ,  H01L29/00

Abstract: A semiconductor substrate includes a buried semiconductor layer and semiconductor wells. A device for detecting a possible thinning of the semiconductor substrate via the rear face thereof is formed on and in the semiconductor wells. The device is a non-inverting buffer including an input terminal and an output terminal, the device being powered between a supply terminal and a reference terminal where the buried semiconductor layer provides the supply terminal. A control circuit delivers an input signal in a first state to the input terminal and outputs a control signal indicating a detection of a thinning of the substrate if a signal generated at the output terminal in response to the input signal is in a second state different from the first state.

公开(公告)号：US11049419B2

公开(公告)日：2021-06-29

申请号：US16186820

申请日：2018-11-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Thomas Ordas ,  Yanis Linge

IPC: G09C1/00 ,  H03K19/003 ,  H04L9/00 ,  G06F21/75

Abstract: In an embodiment, a circuit includes a supply terminal, a reference terminal, a logic circuit coupled between the supply terminal and the reference terminal, and an auxiliary circuit coupled to the logic circuit. The auxiliary circuit includes a plurality of switches configured to be controlled to produce random criterions. Each random criterion causes, on each transition of an output signal of the logic, an attenuation of a current flowing between a supply terminal of the circuit and a reference terminal of the circuit; or an increase of the current flowing between the supply terminal of the circuit and the reference terminal of the circuit; or an additional current flowing through the logic circuit on a current path not passing through the supply terminal; or no change in the current flowing between the supply terminal of the circuit and the reference terminal of the circuit.

公开(公告)号：US10998306B2

公开(公告)日：2021-05-04

申请号：US16100796

申请日：2018-08-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Daniele Fronte ,  Pierre-Yvan Liardet ,  Alexandre Sarafianos

IPC: H01L27/02 ,  G01R31/28 ,  H01L23/00

Abstract: A circuit for protecting an integrated circuit against fault injection attacks includes an element including a dielectric which is destroyed, resulting in the occurrence of a short-circuit. The element is connected between two terminals that receive a power supply voltage of the integrated circuit.

公开(公告)号：US10892234B2

公开(公告)日：2021-01-12

申请号：US16154456

申请日：2018-10-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Abderrezak Marzaki

IPC: H01L23/00 ,  G06F21/87 ,  H04L9/00 ,  H01L29/06 ,  G06F21/78 ,  G06F21/55

Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed, in a first configuration, to detect a thinning of the substrate via its rear face, and in a second configuration, to detect a DFA attack by fault injection into the integrated circuit.

公开(公告)号：US10769513B2

公开(公告)日：2020-09-08

申请号：US16227525

申请日：2018-12-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Thomas Ordas ,  Yanis Linge ,  Jimmy Fort

IPC: G06K19/073 ,  G06F21/75 ,  G06F21/44 ,  H01L23/00

Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.

公开(公告)号：US10473709B2

公开(公告)日：2019-11-12

申请号：US16125096

申请日：2018-09-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Thomas Ordas

IPC: H01L23/00 ,  G01R31/12 ,  G06K19/073 ,  H01L25/065 ,  G01R31/317 ,  H01L23/538

Abstract: An integrated circuit chip stack includes a main integrated circuit chip and at least one auxiliary integrated circuit chip. The main integrated circuit chip contains circuit components to be protected. The auxiliary integrated circuit chip is mounted to a surface of the main integrated circuit chip and includes a metal plane connected to ground located opposite the circuit components to be protected. The auxiliary integrated circuit chip further includes at least one insulated conductive track forming a tight pattern opposite the circuit components to be protected. A detection circuit is connected to the at least one conductive track and is configured to detect interruption of the at least one insulated conductive track.

公开(公告)号：US10345142B2

公开(公告)日：2019-07-09

申请号：US15444529

申请日：2017-02-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Clement Champeix

IPC: G01J1/42 ,  G01J1/44 ,  G06F21/87 ,  H01L23/00 ,  H01L31/112

Abstract: A laser detection device can be used to protect an integrated circuit. The device includes a detection cell having a buried channel of a first conductivity type extending in a substrate of the integrated circuit. The substrate is of a second conductivity type. The detection cell also has a first electrical connection coupling a first point in the buried channel to a supply voltage rail, and a second electrical connection coupled to a second point in the buried channel. A detection circuit is coupled to the second point in the buried channel via the second electrical connection and adapted to detect a fall in the voltage at the second point.