公开(公告)号：US11675721B2

公开(公告)日：2023-06-13

申请号：US17806587

申请日：2022-06-13

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40 ,  G06F11/07 ,  G05B19/042 ,  G06F9/54 ,  H04L12/403 ,  H03M13/09

CPC classification number: G06F13/362 ,  G05B19/042 ,  G06F9/542 ,  G06F11/0739 ,  G06F11/0757 ,  G06F11/0772 ,  G06F13/4068 ,  H04L12/403 ,  G05B2219/1215 ,  G05B2219/2231 ,  G05B2219/31179 ,  H03M13/09

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US20220286319A1

公开(公告)日：2022-09-08

申请号：US17677113

申请日：2022-02-22

Applicant: STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Vaclav Dvorak

IPC: H04L12/403 ,  G06F9/30

Abstract: A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.

公开(公告)号：US11366778B2

公开(公告)日：2022-06-21

申请号：US16874055

申请日：2020-05-14

Applicant: STMICROELECTRONICS DESIGN AND APPLICATION S.R.O. ,  STMICROELECTRONICS APPLICATION GMBH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40 ,  G06F11/07 ,  H04L12/403 ,  G05B19/042 ,  H03M13/09

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US12184448B2

公开(公告)日：2024-12-31

申请号：US18489590

申请日：2023-10-18

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics Design & Application S.R.O.

Inventor： Vaclav Dvorak ,  Fred Rennig

IPC: H04L12/40 ,  G06F13/42

Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.

公开(公告)号：US12088429B2

公开(公告)日：2024-09-10

申请号：US17677113

申请日：2022-02-22

Applicant: STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Vaclav Dvorak

IPC: H04L12/403 ,  H03K7/08 ,  H04L12/40

CPC classification number: H04L12/403 ,  H03K7/08 ,  H04L12/40006 ,  H04L2012/40215

Abstract: A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.

公开(公告)号：US11853252B2

公开(公告)日：2023-12-26

申请号：US17819749

申请日：2022-08-15

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Vaclav Dvorak

IPC: G06F13/42 ,  G06F13/28 ,  G06F13/40 ,  G06F9/30

CPC classification number: G06F13/4282 ,  G06F9/30134 ,  G06F13/28 ,  G06F13/4072

Abstract: A processing system includes a transmission terminal configured to provide a transmission signal, a reception terminal configured to receive a reception signal, a microprocessor programmable via software instructions, a memory controller configured to be connected to a memory, a serial communication interface, and a communication system. Specifically, the serial communication interface supports a CAN FD Light mode of operation and a UART mode of operation. For this purpose, the serial communication interface comprises a control register, a clock management circuit, a transmission shift register, a transmission control circuit, a reception shift register and a reception control circuit. Accordingly, the microprocessor can transmit and/or receive CAN FD Light or UART frames via the same serial communication interface.

公开(公告)号：US20230300001A1

公开(公告)日：2023-09-21

申请号：US18174387

申请日：2023-02-24

Applicant: STMicroelectronics Application GMBH ,  STMICROELECTRONICS DESIGN AND APPLICATION S.R.O. ,  STMicroelectronics S.r.l.

Inventor： Fred Rennig ,  Jochen Barthel ,  Ludek Beran ,  Mirko Dondini ,  Vaclav Dvorak ,  Vincenzo Polisi ,  Marianna Sanza' ,  CalogeroAndrea Trecarichi ,  Alfonso Furio

IPC: H04L12/40 ,  H03K19/00 ,  H03K17/687

CPC classification number: H04L12/40169 ,  H03K19/0002 ,  H03K17/6872 ,  H03K17/6874 ,  H04L12/40032 ,  H04L2012/40273 ,  H04L2012/40215

Abstract: In an embodiment a processing system includes a sub-circuit including a three-state driver circuit, wherein the three-state driver circuit has a combinational logic circuit configured to monitor logic levels of a first signal and a second signal, and selectively activate one of the following switching states as a function of the logic levels of the first signal and the second signal: in a first switching state, connect the transmission terminal to the positive supply terminal by closing the first electronic switch, in a second switching state, connect the transmission terminal to the negative supply terminal by closing the second electronic switch, and in a third switching state, put the transmission terminal in a high-impedance state by opening the first electronic switch and the second electronic switch.

公开(公告)号：US20230053798A1

公开(公告)日：2023-02-23

申请号：US17819749

申请日：2022-08-15

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Vaclav Dvorak

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/28 ,  G06F9/30

Abstract: A processing system includes a transmission terminal configured to provide a transmission signal, a reception terminal configured to receive a reception signal, a microprocessor programmable via software instructions, a memory controller configured to be connected to a memory, a serial communication interface, and a communication system. Specifically, the serial communication interface supports a CAN FD Light mode of operation and a UART mode of operation. For this purpose, the serial communication interface comprises a control register, a clock management circuit, a transmission shift register, a transmission control circuit, a reception shift register and a reception control circuit. Accordingly, the microprocessor can transmit and/or receive CAN FD Light or UART frames via the same serial communication interface.

公开(公告)号：US11526458B2

公开(公告)日：2022-12-13

申请号：US17245894

申请日：2021-04-30

Applicant: STMicroelectronics Application GMBH ,  STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.

Inventor： Fred Rennig ,  Vaclav Dvorak ,  Ludek Beran

IPC: G06F13/362 ,  G06F11/07 ,  H04L12/40 ,  H04L7/00 ,  H04L5/00 ,  G06F13/42 ,  H04L43/55

Abstract: An embodiment method of operating a CAN bus comprises coupling a first device and second devices to the CAN bus via respective CAN transceiver circuits, and configuring the respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of messages via the CAN bus by the respective first device or second devices.

公开(公告)号：US20210357344A1

公开(公告)日：2021-11-18

申请号：US17245894

申请日：2021-04-30

Applicant: STMicroelectronics Application GMBH ,  STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.

Inventor： Fred Rennig ,  Vaclav Dvorak ,  Ludek Beran

IPC: G06F13/362 ,  H04L12/40 ,  G06F11/07

Abstract: An embodiment method of operating a CAN bus comprises coupling a first device and second devices to the CAN bus via respective CAN transceiver circuits, and configuring the respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of messages via the CAN bus by the respective first device or second devices.