公开(公告)号：US12088326B2

公开(公告)日：2024-09-10

申请号：US17940236

申请日：2022-09-08

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Abhishek Jain

IPC: H03M3/00 ,  H03K3/356 ,  H03M1/06

CPC classification number: H03M3/464 ,  H03K3/356 ,  H03M1/0626 ,  H03M3/43

Abstract: A continuous time, sigma-delta analog-to-digital converter circuit includes a sigma-delta modulator circuit configured to receive an analog input signal. A single bit quantizer of the modulator generates a digital output signal at a sampling frequency. A data storage circuit stores bits of the digital output signal and digital-to-analog converter (DAC) elements are actuated in response to the stored bits to generate an analog feedback signal for comparison to the analog input signal. A filter circuit includes polyphase signal processing paths and a summation circuit configured to sum outputs from the polyphase signal processing paths to generate a converted output signal. A fan out circuit selectively applies the stored bits from the data storage circuit to inputs of the polyphase signal processing paths of the filter circuit.

公开(公告)号：US11429478B2

公开(公告)日：2022-08-30

申请号：US16867325

申请日：2020-05-05

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Jain

IPC: G06F11/10 ,  G06F11/30 ,  G06F11/07 ,  G06F11/32 ,  G06F11/16

Abstract: A circuit and methods of operation thereof are provided for robust protection against soft errors. The circuit includes a first set of storage elements coupled to and configured to sample a set of data inputs at a first set of times. The circuit includes a second set of storage elements coupled to and configured to sample the set of data inputs at a second set of times. A first parity generator generates a first parity check for the set of data inputs and a second parity generator generates a second parity check for output of the first set of storage elements. An error correction unit compares the first parity check and the second parity check to detect occurrences of error conditions in the circuit. The error correction unit may control output or operating characteristics of the circuit as a result of error conditions detected.

公开(公告)号：US09160336B2

公开(公告)日：2015-10-13

申请号：US13715721

申请日：2012-12-14

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Jain ,  Chittoor Parthasarathy ,  Kallol Chatterjee

IPC: G06F17/50 ,  H03K19/003

CPC classification number: H03K19/003 ,  G06F17/5045 ,  G06F2217/12 ,  Y02P90/265

Abstract: Disclosed is a system and method for providing a critical path replica system in a circuit. A critical path replica system is created by determining a critical path in a circuit, generating a critical path replica circuit, generating a circuit blueprint, and creating the blueprinted circuit. The circuit comprises a functional logic module having functional logic elements and replica logic modules having logic elements. Each logic element is configured to replicate one or more of the functional logic elements and process a test signal. A replica error detection module analyzes the processed signal to determine whether a timing violation has occurred. In some embodiments, the replica logic module further comprises one or more load modules. A replica controller may modify operation of the circuit based on reported errors. A replica mode select module sets the replica logic module to an aging test mode or a timing sensor mode.

Abstract translation: 公开了一种用于在电路中提供关键路径复制系统的系统和方法。 通过确定电路中的关键路径，产生关键路径复制电路，生成电路蓝图以及创建蓝图电路来创建关键路径复制系统。 该电路包括具有功能逻辑元件的功能逻辑模块和具有逻辑元件的复制逻辑模块。 每个逻辑元件被配置为复制一个或多个功能逻辑元件并处理测试信号。 复制错误检测模块分析处理的信号以确定是否发生定时冲突。 在一些实施例中，副本逻辑模块还包括一个或多个加载模块。 复制控制器可以基于报告的错误来修改电路的操作。 复制模式选择模块将副本逻辑模块设置为老化测试模式或定时传感器模式。

公开(公告)号：US20150169394A1

公开(公告)日：2015-06-18

申请号：US14631128

申请日：2015-02-25

Applicant: STMicroelectronics International N.V.

Inventor： Chittoor Parthasarathy ,  Abhishek Jain

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/1608 ,  H03K3/0375

Abstract: An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.

Abstract translation: 电路的实施例包括数据锁存器和多个级联锁存器，其中多个级联锁存器中的第一个锁存器被配置为从数据锁存器接收第一信号，并且每个后续级联锁存器被配置为接收数据锁存器的数据输出信号 一个先前的级联锁存器和一个错误检测电路，配置成接收相应的数据输出信号，并在此基础上检测级联锁存器工作中的错误。

公开(公告)号：US08570085B2

公开(公告)日：2013-10-29

申请号：US13689476

申请日：2012-11-29

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International NV

Inventor： Andrea Mario Veggetti ,  Abhishek Jain ,  Pankaj Rohilla

IPC: H03K3/289 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/0375 ,  H03K3/356008 ,  H03K19/0016

Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

Abstract translation: 本公开涉及一种具有数据保持功能的低功耗触发器电路，包括至少一个触发器和连接到触发器的输出的至少一个保持单元，并配置为使得在触发器的正常操作期间 电路中，保持单元将触发器的输出端子上存在的数据或逻辑状态发送到其自己的输出端子，而在触发器电路的低功耗操作期间，保持单元的锁存电路适合于存储数据或 激活与触发器的输出端子上存在的最后数据或逻辑状态对应的逻辑状态。

公开(公告)号：US20130088272A1

公开(公告)日：2013-04-11

申请号：US13689476

申请日：2012-11-29

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International NV

Inventor： Andrea Mario Veggetti ,  Abhishek Jain ,  Pankaj Rohilla

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K3/0375 ,  H03K3/356008 ,  H03K19/0016

Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

Abstract translation: 本公开涉及一种具有数据保持功能的低功耗触发器电路，包括至少一个触发器和连接到触发器的输出的至少一个保持单元，并配置为使得在触发器的正常操作期间 电路中，保持单元将触发器的输出端子上存在的数据或逻辑状态发送到其自己的输出端子，而在触发器电路的低功耗操作期间，保持单元的锁存电路适合于存储数据或 激活与触发器的输出端子上存在的最后数据或逻辑状态对应的逻辑状态。