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公开(公告)号：US11068255B2
公开(公告)日：2021-07-20
申请号：US16829280
申请日：2020-03-25
Applicant: STMicroelectronics Application GMBH
Inventor： Roberto Colombo
Abstract: A processing system includes a digital processing unit, one or more non-volatile memories configured to store a firmware to be executed by the digital processing unit, a diagnostic circuit configured to execute a self-test operation of the processing system in response to a diagnostic mode enable signal, and a reset circuit. The reset circuit is configured to perform a complex reset of the processing system by generating a first reset of the processing system in response to a given event and generating a second reset of the processing system once the self-test operation has been executed. The processing system is configured to set the diagnostic mode enable signal in response to the first reset, thereby activating execution of the self-test operation.
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公开(公告)号：US11048525B2
公开(公告)日：2021-06-29
申请号：US16273704
申请日：2019-02-12
Inventor： Roberto Colombo , Om Ranjan
Abstract: A processing system includes a plurality of configuration data clients, each associated with a respective address and including a respective register, and where a respective configuration data client is configured to receive a respective first configuration data and to store the respective first configuration data in the respective register; a hardware block coupled to at least one of the configuration data clients and configured to change operation as a function of the respective first configuration data stored in the respective registers; a non-volatile memory including second configuration data, where the second configuration data are stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients; and a hardware configuration circuit configured to sequentially read the data packets from the non-volatile memory and to transmit the respective first configuration data to the respective configuration data client.
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公开(公告)号：US11977438B2
公开(公告)日：2024-05-07
申请号：US17406910
申请日：2021-08-19
Applicant: STMicroelectronics Application GMBH
Inventor： Roberto Colombo
CPC classification number: G06F11/0784 , G06F11/0721 , G06F11/0739 , G06F11/0751 , G06F11/0772 , G06F11/1048
Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.
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公开(公告)号：US11977424B2
公开(公告)日：2024-05-07
申请号：US17702529
申请日：2022-03-23
Inventor： Roberto Colombo , Nicolas Bernard Grossier
IPC: G06F1/24
CPC classification number: G06F1/24
Abstract: A processing system includes a reset circuit, a memory storing configuration data, and a hardware configuration circuit transmitting the configuration data to configuration data clients. The system executes a reset phase, configuration phase, and software runtime phase. First and second reset terminals are associated with first and second circuitries which are respectively associated with configuration data clients. The configuration data includes first and second mode configuration data for the first and second terminals. During the reset and configuration phase, the first circuitry activates a strong pull-down, and the second circuitry activates a weak pull-down. During the software runtime phase, the first circuitry activate a weak pull-down for implementing a bidirectional reset terminal or activates a weak pull-up resistance for implementing a reset output terminal, and the second circuitry activates a weak pull-up for implementing a reset input terminal or activates a strong pull-up for implementing a reset output terminal.
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公开(公告)号：US20230065623A1
公开(公告)日：2023-03-02
申请号：US17815807
申请日：2022-07-28
Inventor： Vivek Mohan Sharma , Roberto Colombo
Abstract: A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.
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Patent Agency Ranking
公开(公告)号：US20220382695A1
公开(公告)日：2022-12-01
申请号：US17747800
申请日：2022-05-18
Applicant: STMicroelectronics Application GMBH
Inventor： Rolf Nandlinger , Roberto Colombo
Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.
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17.发明授权公开(公告)号：US11032067B2
公开(公告)日：2021-06-08
申请号：US16022110
申请日：2018-06-28
Inventor： Roberto Colombo , Guido Marco Bertoni , William Orlando , Roberta Vittimani
Abstract: A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.
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公开(公告)号：US10949570B2
公开(公告)日：2021-03-16
申请号：US16039103
申请日：2018-07-18
Applicant: STMicroelectronics Application GmbH
Inventor： Roberto Colombo
Abstract: In an embodiment, a processing system includes a non-volatile memory, a hardware block, a protection circuit associated with the hardware block, and a password verification circuit. The non-volatile memory stores at least one reference password. The password verification circuit is configured to receive a password verification command, obtain a reference password, and test whether the passwords correspond. In case the passwords correspond, the password verification circuit generate an overwrite signal. The protection circuit is configured to receive a control command and selectively forward the control command to the associated hardware block as a function of the overwrite signal.
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公开(公告)号：US20200348890A1
公开(公告)日：2020-11-05
申请号：US16932426
申请日：2020-07-17
Applicant: STMicroelectronics Application GmbH
Inventor： Roberto Colombo
Abstract: A processing system comprises a processing unit, a hardware block configured to change operation as a function of life cycle data, and a one-time programmable memory storing original life cycle data. A hardware configuration module is configured to read the original life cycle data from the one-time programmable memory, to store the original life cycle data in a register, to receive a write request from the processing unit, and to selectively execute the write request to overwrite the original life cycle data with new life cycle data in the register.
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公开(公告)号：US20200341836A1
公开(公告)日：2020-10-29
申请号：US16928768
申请日：2020-07-14
Inventor： Roberto Colombo , Nicolas Bernard Grossier , Roberta Vittimani
Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
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