公开(公告)号：US20180342441A1

公开(公告)日：2018-11-29

申请号：US15974456

申请日：2018-05-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Federico Giovanni ZIGLIOLI

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor device including one or more semiconductor dice, a lead frame including an array of signal-carrying leads electrically coupled with the semiconductor die, and a power supply connection for the at least one semiconductor die arranged centrally thereof.

公开(公告)号：US20160315034A1

公开(公告)日：2016-10-27

申请号：US14980546

申请日：2015-12-28

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Federico Giovanni ZIGLIOLI

IPC: H01L23/495 ,  H01L21/683 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/49541 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/568 ,  H01L23/4952 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: An electronic component includes one or more circuits having electrical connections coupled therewith. The electrical connections include a lead frame as well as electrical wires coupling the circuit or circuits to respective portions of the lead frame. The electrical wires may be formed as one piece with the respective portion of the lead frame without joints therebetween, e.g., by 3D printing.

Abstract translation: 电子部件包括具有与其连接的电连接的一个或多个电路。 电连接包括引线框架以及将电路或电路耦合到引线框架的相应部分的电线。 例如，通过3D打印，电线可以与引线框架的相应部分形成为一体而没有接合。

公开(公告)号：US20160223444A1

公开(公告)日：2016-08-04

申请号：US14610068

申请日：2015-01-30

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Alberto PAGANI ,  Bruno MURARI ,  Federico Giovanni ZIGLIOLI

IPC: G01N3/08 ,  H01L21/52 ,  H01L21/56

CPC classification number: G01N3/08 ,  G01L1/005 ,  G01N3/066 ,  H01L23/3107

Abstract: A tensile stress measurement device is to be attached to an object to be measured. The tensile stress measurement device may include an IC having a semiconductor substrate and tensile stress detection circuitry, the semiconductor substrate having opposing first and second attachment areas. The tensile stress measurement device may include a first attachment plate coupled to the first attachment area and extending outwardly to be attached to the object to be measured, and a second attachment plate coupled to the second attachment area and extending outwardly to be attached to the object to be measured. The tensile stress detection circuitry may be configured to detect a tensile stress imparted on the first and second attachment plates when attached to the object to be measured.

Abstract translation: 将拉伸应力测量装置连接到被测量物体上。 拉伸应力测量装置可以包括具有半导体衬底和拉伸应力检测电路的IC，该半导体衬底具有相对的第一和第二附接区域。 拉伸应力测量装置可以包括联接到第一附接区域并向外延伸以连接到待测量物体的第一附接板，以及联接到第二附接区域并向外延伸以附接到物体的第二附接板 待测。 拉伸应力检测电路可以被配置为检测当附接到待测量物体时施加在第一和第二附接板上的拉伸应力。

公开(公告)号：US20210143089A1

公开(公告)日：2021-05-13

申请号：US17155520

申请日：2021-01-22

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Federico Giovanni ZIGLIOLI

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78

Abstract: Embodiments of the present disclosure are directed to flat no-lead packages with wettable sidewalls or flanks. In particular, wettable conductive layers are formed on the package over lateral portions of the leads and on portions of the package body, which may be encapsulation material. The wettable conductive layers may also be formed on bottom surfaces of the package body and the leads. The wettable conductive layers provide a wettable flank for solder to wick up when the package is mounted to a substrate, such as a PCB, using SMT. In particular, solder that is used to join the PCB and the package wicks up the side of the wettable conductive layers along a side surface of the package. In that regard, the solder is exposed and coupled to the side surface of the package at the wettable conductive layers, thereby allowing for a visual inspection of the solder joints. The wettable conductive layers are formed on the package after the package body has been formed. In one embodiment, the wettable conductive layers are printed on the package body and the leads by Aerosol Jet® technology.

公开(公告)号：US20210013134A1

公开(公告)日：2021-01-14

申请号：US17015619

申请日：2020-09-09

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Michele DERAI ,  Federico Giovanni ZIGLIOLI

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate.

公开(公告)号：US20170323834A1

公开(公告)日：2017-11-09

申请号：US15148754

申请日：2016-05-06

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Federico Giovanni ZIGLIOLI

IPC: H01L21/66 ,  H01L23/495 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L22/32 ,  H01L23/3157 ,  H01L23/4951 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: One or more embodiments are directed to semiconductor packages that include conductive test pads that are electrically coupled to, but distinct from, the leads of the package. In one embodiment the test pads are located on the plastic packaging material, such as encapsulation material, of the package and are electrically coupled to the leads of the package by traces. The traces may also be located on the packaging material and portions of the leads. In one embodiment, all of the test pads are located on a single surface of the packaging material of the package, which may allow for ease of electrical testing of the package.

公开(公告)号：US20160172311A1

公开(公告)日：2016-06-16

申请号：US14565934

申请日：2014-12-10

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Alberto PAGANI ,  Giovanni GIRLANDO ,  Federico Giovanni ZIGLIOLI ,  Alessandro FINOCCHIARO

IPC: H01L23/00 ,  G01R31/28 ,  H01L23/528 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L23/562 ,  G01R31/2872 ,  H01L21/76224 ,  H01L22/14 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An IC may include a semiconductor substrate having circuitry formed in the substrate, an interconnect layer above the semiconductor substrate and having an antenna coupled to the circuitry, and a seal ring around a periphery of the interconnect layer. The IC may include an electrically insulating trench extending vertically into the semiconductor substrate and extending laterally across the semiconductor substrate from adjacent one side to adjacent another side.

Abstract translation: IC可以包括具有形成在衬底中的电路的半导体衬底，在半导体衬底上方的互连层，并且具有耦合到电路的天线以及围绕互连层周围的密封环。 IC可以包括垂直延伸到半导体衬底中的电绝缘沟槽，并且从相邻的一侧横向跨越半导体衬底延伸到相邻的另一侧。

公开(公告)号：US20130243143A1

公开(公告)日：2013-09-19

申请号：US13775444

申请日：2013-02-25

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ubaldo MASTROMATTEO ,  Federico Giovanni ZIGLIOLI

IPC: G21B3/00

CPC classification number: G21B3/002

Abstract: An embodiment of an apparatus includes a reaction chamber, a reaction unit, and an energy regulator. The reaction chamber includes an energy port, and the reaction unit is disposed in the reaction chamber and is configured to allow an energy-releasing reaction between first and second materials. And the energy regulator is configured to control a rate at which reaction-released energy exits the reaction chamber via the energy port. The reaction chamber may include a thermally conductive wall that forms a portion of the energy port, and the energy regulator may include a thermally conductive member and a mechanism configured to control a distance between the thermally conductive wall and the thermally conductive member. Furthermore, the reaction unit may include a mechanism configured to facilitate the reaction between the first and second materials, and may also include a mechanism configured to control a rate at which the reaction releases energy.

Abstract translation: 装置的实施例包括反应室，反应单元和能量调节器。 反应室包括能量口，并且反应单元设置在反应室中并且构造成允许第一和第二材料之间的能量释放反应。 并且能量调节器被配置为控制反应释放的能量经由能量端口离开反应室的速率。 反应室可以包括形成能量端口的一部分的导热壁，并且能量调节器可以包括导热构件和构造成控制导热壁和导热构件之间的距离的机构。 此外，反应单元可以包括构造成促进第一和第二材料之间的反应的机构，并且还可以包括被配置为控制反应释放能量的速率的机构。

公开(公告)号：US20210050299A1

公开(公告)日：2021-02-18

申请号：US16990748

申请日：2020-08-11

Applicant: STMicroelectronics S.r.l.

Inventor： Federico Giovanni ZIGLIOLI ,  Alberto PINTUS ,  Michele DERAI ,  Pierangelo MAGNI

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/66 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A method of manufacturing semiconductor devices, such as integrated circuits includes arranging one or more semiconductor dice on a support surface. Laser direct structuring material is molded onto the support surface having the semiconductor die/dice arranged thereon. Laser beam processing is performed on the laser direct structuring material molded onto the support surface having the semiconductor die/dice arranged thereon to provide electrically conductive formations for the semiconductor die/dice arranged on the support surface. The semiconductor die/dice provided with the electrically-conductive formations are separated from the support surface.

公开(公告)号：US20190181076A1

公开(公告)日：2019-06-13

申请号：US16213540

申请日：2018-12-07

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Dario VITELLO ,  Fabio MARCHISI ,  Alberto ARRIGONI ,  Federico FREGO ,  Federico Giovanni ZIGLIOLI ,  Paolo CREMA

IPC: H01L23/495 ,  H01L21/48 ,  B26F1/38 ,  B23C3/13 ,  C23F1/02

Abstract: A method of producing leadframes for semiconductor devices comprises: providing a plurality of electrically-conductive plates, forming in the electrically conductive plates homologous passageway patterns according to a desired semiconductor device leadframe pattern, joining together the plurality of plates with the homologous passageway patterns formed therein mutually in register by producing a multilayered leadframe exhibiting the desired leadframe pattern and a thickness which is the sum of the thicknesses of the plates in the plurality of electrically-conductive plates.