公开(公告)号：US20180358456A1

公开(公告)日：2018-12-13

申请号：US16004257

申请日：2018-06-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando IUCOLANO ,  Alessandro CHINI

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/778 ,  H01L29/0847 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: An HEMT includes a buffer layer, a hole-supply layer on the buffer layer, a heterostructure on the hole-supply layer, and a source electrode. The hole-supply layer is made of P-type doped semiconductor material, the buffer layer is doped with carbon, and the source electrode is in direct electrical contact with the hole-supply layer, such that the hole-supply layer can be biased to facilitate the transport of holes from the hole-supply layer to the buffer layer.

公开(公告)号：US20250040164A1

公开(公告)日：2025-01-30

申请号：US18910960

申请日：2024-10-09

Applicant: STMicroelectronics S.r.l.

Inventor： Ferdinando IUCOLANO ,  Cristina TRINGALI

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

Abstract: A method for manufacturing an ohmic contact for a HEMT device, comprising the steps of: forming a photoresist layer, on a semiconductor body comprising a heterostructure; forming, in the photoresist layer, an opening, through which a surface region of the semiconductor body is exposed at said heterostructure; etching the surface region of the semiconductor body using the photoresist layer as etching mask to form a trench in the heterostructure; depositing one or more metal layers in said trench and on the photoresist layer; and carrying out a process of lift-off of the photoresist layer.

公开(公告)号：US20230246086A1

公开(公告)日：2023-08-03

申请号：US18156120

申请日：2023-01-18

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Ferdinando IUCOLANO ,  Raffaella LO NIGRO ,  Emanuela SCHILIRÒ ,  Fabrizio ROCCAFORTE

IPC: H01L29/51 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/02 ,  H01L21/28 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/513 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/28185 ,  H01L29/205 ,  H01L29/401 ,  H01L29/517 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/66462

Abstract: The present disclosure is directed to a wide band gap transistor that includes a semiconductor structure, having at least one wide band gap semiconductor layer of gallium nitride or silicon carbide, an insulating gate structure and a gate electrode, separated from the semiconductor structure by the insulating gate structure. The insulating gate structure contains a mixture of aluminum, hafnium and oxygen.

公开(公告)号：US20220013982A1

公开(公告)日：2022-01-13

申请号：US17368554

申请日：2021-07-06

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Antonio Filippo Massimo PIZZARDI ,  Santo Alessandro SMERZI ,  Ferdinando IUCOLANO ,  Romeo LETOR

IPC: H01S5/042 ,  G01S7/481 ,  G01S7/484 ,  H01S5/40

Abstract: An electronic device is couplable to a plurality of laser diodes and includes a control switch having a drain coupled to a drain metallization and having a source coupled to a first source metallization that is electrically couplable to cathodes of the laser diodes. Each of a plurality of first switches has a drain coupled to the drain metallization and a source coupled to a respective second source metallization that is couplable to an anode of the laser diodes. The second source metallizations are aligned with one another in a direction of alignment, overlie, in a direction orthogonal to the direction of alignment, the respective sources of the first switches, and can be aligned, in a direction orthogonal to the direction of alignment, to the respective laser diodes. At least one of the sources of the first switches can be aligned, in a direction orthogonal to the direction of alignment, to the respective laser diode.

公开(公告)号：US20210313446A1

公开(公告)日：2021-10-07

申请号：US17350916

申请日：2021-06-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando IUCOLANO ,  Paolo BADALÁ

IPC: H01L29/66 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/778

Abstract: An HEMT device of a normally-on type, comprising a heterostructure; a dielectric layer extending over the heterostructure; and a gate electrode extending right through the dielectric layer. The gate electrode is a stack, which includes: a protection layer, which is made of a metal nitride with stuffed grain boundaries and extends over the heterostructure, and a first metal layer, which extends over the protection layer and is completely separated from the heterostructure by said protection layer.

公开(公告)号：US20210091205A1

公开(公告)日：2021-03-25

申请号：US17118439

申请日：2020-12-10

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Ferdinando IUCOLANO

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/778 ,  H01L21/324 ,  H01L21/225 ,  H01L29/20

Abstract: A manufacturing method of an HEMT includes: forming a heterostructure; forming a first gate layer of intrinsic semiconductor material on the heterostructure; forming a second gate layer, containing dopant impurities of a P type, on the first gate layer; removing first portions of the second gate layer so that second portions, not removed, of the second gate layer form a doped gate region; and carrying out a thermal annealing of the doped gate region so as to cause a diffusion of said dopant impurities of the P type in the first gate layer and in the heterostructure, with a concentration, in the heterostructure, that decreases as the lateral distance from the doped gate region increases.

公开(公告)号：US20200168718A1

公开(公告)日：2020-05-28

申请号：US16697051

申请日：2019-11-26

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando IUCOLANO ,  Cristina TRINGALI

IPC: H01L29/66 ,  H01L29/778

Abstract: A method for manufacturing an ohmic contact for a HEMT device, comprising the steps of: forming a photoresist layer, on a semiconductor body comprising a heterostructure; forming, in the photoresist layer, an opening, through which a surface region of the semiconductor body is exposed at said heterostructure; etching the surface region of the semiconductor body using the photoresist layer as etching mask to form a trench in the heterostructure; depositing one or more metal layers in said trench and on the photoresist layer; and carrying out a process of lift-off of the photoresist layer.

公开(公告)号：US20200152779A1

公开(公告)日：2020-05-14

申请号：US16738935

申请日：2020-01-09

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando IUCOLANO ,  Giuseppe GRECO ,  Fabrizio ROCCAFORTE

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L23/29 ,  H01L23/31

Abstract: A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.

公开(公告)号：US20200152572A1

公开(公告)日：2020-05-14

申请号：US16676371

申请日：2019-11-06

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Santo Alessandro SMERZI ,  Maria Concetta NICOTRA ,  Ferdinando IUCOLANO

IPC: H01L23/528 ,  H01L23/522

Abstract: An electronic device, comprising plurality of source metal strips in a first metal level; a plurality of drain metal strips in the first metal level; a source metal bus in a second metal level above the first metal level; a drain metal bus, in the second metal level; a source pad, coupled to the source metal bus; and a drain pad, coupled to the drain metal bus. The source metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the first conductive pad; the drain metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the second conductive pad. The first and second subregions are interdigitated.

公开(公告)号：US20240162153A1

公开(公告)日：2024-05-16

申请号：US18509052

申请日：2023-11-14

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Santo Alessandro SMERZI ,  Maria Concetta NICOTRA ,  Ferdinando IUCOLANO

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/5226 ,  H01L29/2003

Abstract: An electronic device, comprising plurality of source metal strips in a first metal level; a plurality of drain metal strips in the first metal level; a source metal bus in a second metal level above the first metal level; a drain metal bus, in the second metal level; a source pad, coupled to the source metal bus; and a drain pad, coupled to the drain metal bus. The source metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the first conductive pad; the drain metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the second conductive pad. The first and second subregions are interdigitated.