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11.发明授权公开(公告)号：US11093658B2
公开(公告)日：2021-08-17
申请号：US15975460
申请日：2018-05-09
IPC分类号： G06F21/83 , G06F21/64 , G06F12/02 , G06F9/38 , G06F9/445 , H04L9/32 , G06F21/57 , G09C1/00 , G06F21/74 , H04W12/106 , H04L29/06 , H04W4/40 , H04W12/03 , H04W12/40
摘要： A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.
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公开(公告)号：US11057194B2
公开(公告)日：2021-07-06
申请号：US16022033
申请日：2018-06-28
摘要： A processing system includes a first processing unit; a second processing unit; and a cryptographic coprocessor communicatively coupled to the first processing unit and the second processing unit. The cryptographic coprocessor includes a key storage memory for storing a cryptographic key; a first interface configured to receive source data to be processed directly from the first processing unit; a hardware cryptographic engine configured to process the source data as a function of the cryptographic key stored in the key storage memory; a second interface configured to receive a first cryptographic key directly from the second processing unit; and a hardware key management circuit configured to store the first cryptographic key in the key storage memory.
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公开(公告)号：US12068057B2
公开(公告)日：2024-08-20
申请号：US18056803
申请日：2022-11-18
申请人： STMicroelectronics S.r.l. , STMicroelectronics International N.V. , STMicroelectronics Application GMBH
CPC分类号： G11C7/24 , G11C7/1039 , G11C7/1069
摘要： In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.
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公开(公告)号：US11210161B2
公开(公告)日：2021-12-28
申请号：US16928768
申请日：2020-07-14
摘要： In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
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15.发明授权公开(公告)号：US12117949B2
公开(公告)日：2024-10-15
申请号：US18364786
申请日：2023-08-03
发明人： Rolf Nandlinger , Roberto Colombo
CPC分类号： G06F13/28 , G06F9/30105 , G06F9/3877 , G06F13/4282 , G06F21/602 , G06F21/72
摘要： In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.
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公开(公告)号：US11822934B2
公开(公告)日：2023-11-21
申请号：US17341054
申请日：2021-06-07
发明人： Roberto Colombo , Om Ranjan
CPC分类号： G06F9/44505 , G06F11/1004 , G06F13/36 , H04L9/0643 , H04L9/3247
摘要： A processing system includes a plurality of configuration data clients; each associated with a respective address and including a respective register, a hardware block, a non-volatile memory, and a hardware configuration circuit. A respective configuration data client receives a respective first configuration data and stores it in the respective register. The hardware block is coupled to at least one of the configuration data clients and changes operation as a function of the respective first configuration data stored in the respective registers. The non-volatile memory includes second configuration data stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients. The hardware configuration circuit sequentially reads the data packets from the non-volatile memory and transmits the respective first configuration data to the respective configuration data client.
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公开(公告)号：US11764807B2
公开(公告)日：2023-09-19
申请号：US17858782
申请日：2022-07-06
CPC分类号： H03M13/1105 , H03M13/611
摘要： A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits. For example the safety monitor circuit comprises a test circuit configured to provide modified data bits and/or modified ECC bits to the error detection circuit as a function of connectivity test control signals, whereby the error detection circuit asserts the error signal as a function of the connectivity test control signals. The processing system comprises also a connectivity test control circuit comprising control registers programmable via the microprocessor, wherein the connectivity test control signals are generated as a function of the content of the control registers.
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公开(公告)号：US20220334865A1
公开(公告)日：2022-10-20
申请号：US17657856
申请日：2022-04-04
摘要： A processing system includes safety monitoring circuits configured to generate error signals by monitoring a microprocessor operations, a memory controller, and/or a resource. The system further includes fault collection sub-circuits, each including one or more error combination circuits, each including a first programmable register and being configured to receive a subset of the error signals, determine whether an error signal is asserted, and store to the first register error status data that identifies the asserted error signal. Each error combination circuit is configured to read enable data from the first register and generate a combined error signal based on the error status and enable data. The error management circuit includes a second programmable register and is configured to receive the combined error signals, read routing data from the second register, and generate for each microprocessor an error signal based on the combined error signals and routing data.
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公开(公告)号：US11068255B2
公开(公告)日：2021-07-20
申请号：US16829280
申请日：2020-03-25
发明人： Roberto Colombo
IPC分类号： G06F9/44 , G06F21/57 , G06F9/445 , G06F1/24 , G06F9/4401 , G06F8/654 , G06F11/27 , G06F12/10
摘要： A processing system includes a digital processing unit, one or more non-volatile memories configured to store a firmware to be executed by the digital processing unit, a diagnostic circuit configured to execute a self-test operation of the processing system in response to a diagnostic mode enable signal, and a reset circuit. The reset circuit is configured to perform a complex reset of the processing system by generating a first reset of the processing system in response to a given event and generating a second reset of the processing system once the self-test operation has been executed. The processing system is configured to set the diagnostic mode enable signal in response to the first reset, thereby activating execution of the self-test operation.
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公开(公告)号：US11048525B2
公开(公告)日：2021-06-29
申请号：US16273704
申请日：2019-02-12
发明人： Roberto Colombo , Om Ranjan
摘要： A processing system includes a plurality of configuration data clients, each associated with a respective address and including a respective register, and where a respective configuration data client is configured to receive a respective first configuration data and to store the respective first configuration data in the respective register; a hardware block coupled to at least one of the configuration data clients and configured to change operation as a function of the respective first configuration data stored in the respective registers; a non-volatile memory including second configuration data, where the second configuration data are stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients; and a hardware configuration circuit configured to sequentially read the data packets from the non-volatile memory and to transmit the respective first configuration data to the respective configuration data client.
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