公开(公告)号：US5841155A

公开(公告)日：1998-11-24

申请号：US597228

申请日：1996-02-06

申请人： Yoshio Terasawa

发明人： Yoshio Terasawa

IPC分类号： H01L21/18 ,  H01L21/329 ,  H01L21/331 ,  H01L21/332 ,  H01L21/336 ,  H01L29/423 ,  H01L29/739 ,  H01L29/744 ,  H01L29/78 ,  H01L29/74

CPC分类号： H01L29/7397 ,  H01L21/187 ,  H01L29/66348 ,  H01L29/66356 ,  H01L29/66371 ,  H01L29/7392 ,  H01L29/744 ,  H01L29/7813 ,  H01L29/4232 ,  H01L29/4238 ,  Y10S148/012

摘要： A method of manufacturing a joined-type semiconductor device having a gate structure. The semiconductor device includes a first and second semiconductor substrates each having a substrate body, and a first and a second main surfaces which are opposite to each other. A gate structure is formed in the first main surface of the first substrate. A highly-doped semiconductor layer is formed in the first main surface of the second substrate and has an impurity-concentration which is higher than that of the substrate body of the second substrate. The first main surfaces of the two substrates are joined with each other, by subjecting the two substrates to a heat treatment so that impurities in the highly-doped semiconductor layer of the second substrate are driven into the surface region of the first substrate, and a diffusion layer is thereby formed in the first main surface of the first substrate.

摘要翻译： 一种具有栅极结构的接合型半导体器件的制造方法。 半导体器件包括每个具有基板主体的第一和第二半导体基板以及彼此相对的第一主表面和第二主表面。 栅极结构形成在第一基板的第一主表面中。 在第二基板的第一主表面上形成高掺杂半导体层，其杂质浓度高于第二基板的基板本体的杂质浓度。 通过对两个基板进行热处理，使第二基板的高掺杂半导体层中的杂质被驱动到第一基板的表面区域中，使两个基板的第一主表面相互连接， 从而在第一基板的第一主表面上形成扩散层。

公开(公告)号：US5757035A

公开(公告)日：1998-05-26

申请号：US772884

申请日：1996-12-24

申请人： Yoshio Terasawa

发明人： Yoshio Terasawa

IPC分类号： H01L29/739 ,  H01L29/74 ,  H01L29/744

CPC分类号： H01L29/744 ,  H01L29/7392

摘要： In a surface of a silicon substrate of one conductivity type, there are formed a plurality of depressions or recesses, gate regions of opposite conductivity type are formed at bottoms of respective recesses, gate electrodes are provided on respective gate regions, and an electrically conductive block is joined to the surface of the semiconductor substrate. Between the surface of the semiconductor substrate and the electrically conductive block a contact region having a high impurity concentration and/or an electrically conductive material layer may be provided in order to improve electrical and mechanical properties of the contact between the semiconductor substrate and the electrically conductive block. The gate region can have a high impurity concentration and a distance between a channel region and the electrically conductive block can be very small.

摘要翻译： 在一种导电类型的硅衬底的表面中，形成多个凹陷或凹陷，在各个凹部的底部形成相反导电类型的栅极区，在各个栅极区上设置栅电极，并且导电块 连接到半导体衬底的表面。 在半导体衬底的表面和导电块之间可以提供具有高杂质浓度的接触区域和/或导电材料层，以便改善半导体衬底与导电之间的接触的电学和机械性能 块。 栅极区域可以具有高的杂质浓度，并且沟道区域和导电块之间的距离可以非常小。

公开(公告)号：US4223328A

公开(公告)日：1980-09-16

申请号：US911311

申请日：1978-06-01

申请人： Yoshio Terasawa ,  Kenji Miyata ,  Masayoshi Naito ,  Takuzo Ogawa ,  Masahiro Okamura

发明人： Yoshio Terasawa ,  Kenji Miyata ,  Masayoshi Naito ,  Takuzo Ogawa ,  Masahiro Okamura

IPC分类号： H01L29/80 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/74 ,  H01L29/744

CPC分类号： H01L29/744 ,  H01L29/0834 ,  H01L29/1066 ,  H01L29/167

摘要： A field controlled thyristor is disclosed which comprises a first emitter region exposed to one main surface of a semiconductor substrate and having a first conductivity type, a second emitter region exposed to the other main surface of the substrate and having a second conductivity type, a base region connecting the first and the second emitter region, and a gate region provided in the base region. The gate region consists of a slab-like first portion disposed parallel to both the emitter and a second portion connecting the first slab-like portion with one of the main surfaces of the semiconductor substrate. The impurity concentration of the base region is higher in the portion of the base region nearer to the emitter region having the same conductivity type as that of the base region than in the portion of the base region nearer to the emitter region having the opposite conductivity type to that of the base region. The field controlled thyristor has a high forward blocking voltage gain (anode-cathode voltage/gate bias voltage), a large current rating, and a high switching power capability and its switching time is very short.

摘要翻译： 公开了一种场控晶闸管，其包括暴露于半导体衬底的一个主表面并具有第一导电类型的第一发射极区域，暴露于衬底的另一个主表面并具有第二导电类型的第二发射极区域， 连接第一和第二发射极区域的区域，以及设置在基极区域中的栅极区域。 栅极区域由平行于发射极的板状第一部分和将第一板状部分与半导体衬底的主表面中的一个连接的第二部分组成。 基极区域的杂质浓度比基极区域具有与基极区域相同的导电类型的发射极区域的部分比在具有相反导电类型的发射极区域更靠近的部分的基极区域更高 到基地区。 场控晶闸管具有高正向阻断电压增益（阳极 - 阴极电压/栅极偏置电压），大额定电流和高开关功率能力，其开关时间非常短。

公开(公告)号：US6159776A

公开(公告)日：2000-12-12

申请号：US167560

申请日：1998-10-07

申请人： Yoshio Terasawa

发明人： Yoshio Terasawa

IPC分类号： H01L29/74 ,  H01L21/329 ,  H01L29/739 ,  H01L21/332

CPC分类号： H01L29/66356 ,  H01L29/7392

摘要： A normally-off semiconductor device with gate regions formed in a high-quality base is manufactured by forming a P.sup.+ layer in a lower surface of an N.sup.- substrate, selectively forming P.sup.+ gate regions in an upper surface of the N.sup.- substrate, forming intergate P.sup.+ regions in the upper surface of the N.sup.- substrate between the P.sup.+ gate regions, forming an N.sup.+ layer in an upper surface of an N.sup.- substrate, joining the N.sup.- substrate and the N.sup.- substrate to each other by heating them at about 800.degree. C. in a hydrogen atmosphere while the upper surface of the N.sup.- substrate and a lower surface of the N.sup.- substrate are being held against each other, and forming an anode electrode and a cathode electrode.

摘要翻译： 通过在N基板的下表面中形成P +层，在N基板的上表面中选择性地形成P +栅极区域，制造在高品质基底上形成有栅极区域的常关半导体器件，形成栅极 P +栅极区域之间的N衬底的上表面中的P +区域，在N衬底的上表面中形成N +层，通过将N-衬底和N衬底彼此加热，以约800 在N基板的上表面和N基板的下表面彼此保持的同时，形成阳极电极和阴极电极。

公开(公告)号：US4114178A

公开(公告)日：1978-09-12

申请号：US652662

申请日：1976-01-27

申请人： Yoshio Terasawa ,  Shin Kimura

发明人： Yoshio Terasawa ,  Shin Kimura

IPC分类号： H01L29/41 ,  H01L29/74

CPC分类号： H01L29/7428 ,  H01L29/41

摘要： A semiconductor controlled rectifier comprising a semiconductor substrate consisting of four layers doped alternately with p- and n-type impurities, a pair of main electrodes kept in ohmic contact with the outermost p- and n-type layers, an N auxiliary region in the intermediate p-type layer with an auxiliary contact thereto, and a gate electrode in contact with the intermediate p-type layer, wherein a portion of the gate electrode is disposed adjacent to the auxiliary region, where there are localized regions forming low resistance paths between the gate electrode and the auxiliary electrode.

公开(公告)号：US4016591A

公开(公告)日：1977-04-05

申请号：US515029

申请日：1974-10-15

申请人： Yoshio Terasawa

发明人： Yoshio Terasawa

IPC分类号： H01L29/00 ,  H01L29/10 ,  H01L29/417 ,  H01L29/74

CPC分类号： H01L29/417 ,  H01L29/00 ,  H01L29/10 ,  H01L29/74

摘要： A semiconductor controlled rectifier comprising a semiconductor substrate having four layers of PNPN types, a pair of main electrodes respectively in ohmic contact with the opposite outer layers, a gate electrode provided to the intermediate P-type layer, a N-type auxiliary region formed in the P-type intermediate layer at such a location that the gate electrode is positioned between the outer N-type layer and the auxiliary region, an auxiliary electrode in contact with the auxiliary region and the P-type intermediate layer, and means for short-circuiting a part of a PN junction formed between the N-type outer layer and the P-type intermediate layer.

摘要翻译： 一种半导体可控整流器，包括具有四层PNPN类型的半导体衬底，分别与相对的外层欧姆接触的一对主电极，设置在中间P型层的栅电极，形成在中间P型层中的N型辅助区 在栅极位于外部N型层和辅助区之间的位置处的P型中间层，与辅助区接触的辅助电极和P型中间层， 电路形成在N型外层和P型中间层之间的PN结的一部分。

公开(公告)号：US3978513A

公开(公告)日：1976-08-31

申请号：US487723

申请日：1974-07-11

申请人： Yoshio Terasawa

发明人： Yoshio Terasawa

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/74

CPC分类号： H01L29/74 ,  H01L29/0692 ,  H01L29/42308

摘要： A semiconductor controlled rectifying device comprising a substrate having a four-layer structure wherein first and second regions are formed in one of the outermost layers of the structure and wherein a gate electrode is provided between the first and second regions.

公开(公告)号：US3943548A

公开(公告)日：1976-03-09

申请号：US439698

申请日：1974-02-05

申请人： Yoshio Terasawa

发明人： Yoshio Terasawa

IPC分类号： H01L29/74 ,  H01L29/00 ,  H01L29/10

CPC分类号： H01L29/00 ,  H01L29/10

摘要： A semiconductor controlled rectifier comprising a four-layer semicondcutor substrate of pnpn structure, a pair of main electrodes in contact with the outer p-type and n-type layers respectively, and a gate electrode in contact with one of the intermediate layers forming a pn junction between it and the outer layer adjacent thereto, wherein gate current supplied from the gate electrode flows into the outer layer adjacent to the intermediate layer having the gate electrode thereon across a portion of the pn junction which portion is parallel with the surface of the said outer layer in contact with the main electrode.

摘要翻译： 一种半导体可控整流器，包括pnpn结构的四层半切割器基板，分别与外部p型和n型层接触的一对主电极以及与形成pn的中间层之一接触的栅电极 其与其相邻的外层之间的接合，其中从栅电极提供的栅极电流流过与其上具有栅电极的中间层相邻的外层，跨越pn结的该部分平行于所述 外层与主电极接触。

公开(公告)号：US5946572A

公开(公告)日：1999-08-31

申请号：US203476

申请日：1998-12-02

申请人： Yoshio Terasawa

发明人： Yoshio Terasawa

IPC分类号： H01L29/744 ,  H01L21/329 ,  H01L21/331 ,  H01L21/332 ,  H01L21/336 ,  H01L29/739 ,  H01L29/74 ,  H01L29/772 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66356 ,  H01L29/66348 ,  H01L29/66378 ,  H01L29/7392 ,  H01L29/7722

摘要： A gate structure including semiconductor regions each having a high impurity-concentration and being formed within respective one of recessed portions provided in a surface of a first semiconductor substrate, and then a second semiconductor substrate is brought into contact with the surface of the first semiconductor substrate. The gate structure may be formed such that each of the recessed portions is completely or partially filled with the gate structure. When the gate structure includes electrically good-conductive films of a high melting point metal or the like each formed in respective one of the recessed portions, the gate resistance can be further decreased.

摘要翻译： 一种栅极结构，其包括各自具有高杂质浓度的半导体区域，并且形成在设置在第一半导体衬底的表面中的凹部中的相应一个中，然后使第二半导体衬底与第一半导体衬底的表面接触 。 栅极结构可以形成为使得每个凹部完全或部分地填充有栅极结构。 当栅极结构包括形成在各个凹部中的高熔点金属等的导电性良好的导电膜时，可以进一步降低栅极电阻。

公开(公告)号：US5739044A

公开(公告)日：1998-04-14

申请号：US728147

申请日：1996-10-09

申请人： Yoshio Terasawa

发明人： Yoshio Terasawa

IPC分类号： H01L29/744 ,  H01L21/329 ,  H01L21/332 ,  H01L21/335 ,  H01L29/739 ,  H01L29/74 ,  H01L29/80 ,  H01L21/265 ,  H01L49/00

CPC分类号： H01L29/66356 ,  H01L29/66363 ,  H01L29/66416 ,  H01L29/739

摘要： After selectively forming P.sub.+ -type gate regions 14 in the upper surface of a first N.sup.- -type semiconductor substrate 10, gate electrodes 30 are selectively formed on the P.sup.+ -type gate regions. A P.sup.+ -type layer 12 is formed in the lower surface of the N.sup.- -type substrate 10. Recessed portions 26 which can house the gate electrodes are formed in the lower surface of the second N.sup.- -type semiconductor substrate 20 and an N.sup.+ -type layer 22 is formed in the upper surface thereof. After removing impurities from the surfaces of the first and second semiconductor substrates 10 and 20 by RCA cleaning, the surfaces are cleaned with a pure water and are dried by a spinner. Then the substrates 10 and 20 are joined to each other by heating the substrates 10 and 20 at 700.degree.-1100.degree. C. in an H.sub.2 atmosphere, while the upper surface of the first semiconductor substrate 10 is brought into contact with projected portions 29 on the lower surface of the second semiconductor substrate 20. Thus there can be obtained a static induction thyristor, static induction transistor or gate turn-off thyristor, in each of which gate regions and gate electrodes are buried within a semiconductor substrate.

摘要翻译： 在第一N型半导体衬底10的上表面中选择性地形成P +型栅极区14之后，选择性地在P +型栅极区上形成栅电极30。 在N型基板10的下表面上形成有P +型层12.在第二N型半导体基板20的下表面形成有能够容纳栅电极的凹部26，N + 型层22在其上表面形成。 在通过RCA清洁从第一和第二半导体衬底10和20的表面除去杂质之后，用纯水清洗表面并用旋转器干燥。 然后通过在H 2气氛中在700°-111℃下加热衬底10和20，将衬底10和20彼此接合，同时使第一半导体衬底10的上表面与突出部分29接触 第二半导体衬底20的下表面。因此，可以获得静态感应晶闸管，静电感应晶体管或栅极截止晶闸管，其中每个栅极区域和栅电极被掩埋在半导体衬底内。